4 May
2013
4 May
'13
7:42 p.m.
On Sun, May 05, 2013 at 01:29:29AM +0200, Sytse van Slooten wrote:
The next step will have to be instrumenting the RP core
such that I can have
my logic analyzer capture the commands and register access to it - then we can
compare the results from e11 or simh with the fpga. Adding that kind of
instrumentation is a lot of work though - I was hoping to avoid it. But unless
I get a new insight, it's going to be the only way.
Maybe breakpoints would make this easier? I.e. trace out the code so there
are a few places where you know it's happy so far, and see if you're hitting
them. I would assume that it wouldn't be too difficult to compile a hacked
version of the FPGA code with a temporarily hard-coded PC value that it checks
for on each fetch and halts or asserts a GPIO or otherwise lets you know. Then
you keep doing that until you find a place where the SW and HW emulations
disagree. Tedious but still maybe still easier than extending the RH/DCL code
to dump its guts all the time?
John Wilson
D Bit