On 02.01.2014 22:40, Paul Koning wrote:
I don?t know Verilog, but if it really is PERL-like
that?s quite a strong condemnation.
It's [something unspeakable]
VHDL is clearly inspired by Ada.
It is not only
inspired: it's a superset! I once compiled a VHDL package using
an ADA compiler - just for fun - it just worked and did not complain.
I?ve done some elementary VHDL work and like it a
lot.
:-)
No matter the syntax, an HDL is a very different beast
than a programming languages.
It's like programming in god mode: When you
program a computer you have to use
the computer's resources to get your problem solved. The way the computer design
allows you. In VLSI design there is no computer - things just happen.
If you don?t know that changes to a VHDL ?signal? are
not visible until the next model cycle, you won?t get very far...
First level: No
clue of digital stuff
second level: Ah, it works! But never mix signals with variables! Bad things
will happen!
Next level: There's nothing better than mixing signal and variable assignments.
Is there anything wrong with it?
:-)
--
Dipl.-Inf. (FH) Philipp Hachtmann
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philipp at
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