15 Oct
2012
15 Oct
'12
11:31 a.m.
On 10/14/12 8:40 PM, Eric Smith wrote:
I wrote:
With a discrete design, the propagation delay is likely to go up. Is there
a maximum prop delay criteria?
meeting the maximum leakage current spec is quite
difficult.
Dave McGuire wrote:
Why? (if you want to go into it)
The requirements are basically:
Vol 0.7V max into 70 mA load
Vil max 1.3V
Vih min 1.7V
minimum 5 ns rise and fall times (10% to 90%)
80uA max leakage at 3.8V, 10uA max at 0V (with Vcc from 0.0V to 5.25V)
10pF max capacitance
My attempts to design anything that meets this failed on either the leakage current,
capacitive
loading, or both. However, someone who is more skilled with analog design could probably
come up
with something satisfactory.
Even the National DS8641 and DS3662 didn't quite meet the requirements. It is
unclear whether the
ones DEC used had been screened to better specs (either by National or DEC).