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Although, with
the 3 SPC slots - although they are on UNIBUS A, and only
UNIBUS B has the 18-bit capability
It is of course perfectly possible to run UNIBUS _A_ (where the SPC slots are)
in 18-bit mode too - although the _RH11_ can't use it that way. But you won't
be using the RH11 anyway, so who cares?
Also, I took another look at the KS10 tech manual, and they do in fact use use
an M9200 'thin' jumper (although it's mis-labelled "M9300" in the
diagram -
that diagram has a number of errors, including the "M8014" in the UNIBUS
'A'
In slot - they must mean an M9014 [UNIBUS to 3 flat cables] instead) to link
the two UNIBI together. Which answers the question of how the KS10 CPU gained
access to UNIBUS A (where the device registers, interrupts, etc are) when it
also had to be connected to UNIBUS B (for 18-bit data transfers).
So I think all our questions are answerered (except for the -AB/-C difference
issue).
So I understand right:
UniBone can be used in UNIBUS-A SPC slots in 18 bit mode without any extra adapters?
And can emulate an RH11-C there, even if the RH11 is supposed to run in UNIBUS B?
Thats good news.
Two more things to check:
1. We've seen early SPC slots (PDP-11/40, '45) without NPG wired,
'cause SPC was apparently originally meant for "Small" peripherals without
DMA.
Is KS10 UNIBUS-A wired to be DMA capable?
2. When doing 18bit on UNIBUS-A we put all kind of signal levels
on parity lines PA,PB = DATA<16:17>.
Won't the KS10 CPU interpret these as real BUS parity errors generated
by some UNIBUS-A device?
best regards
Joerg