On Jan 6, 2014, at 07:04 , dwight <dkelvey at hotmail.com> wrote:
Reading Verilog or HDL that two different people have
written where
they've switched from positive to negative logic and back is a pain.
That reminds me of a guy I worked with back in the 90s. He inherited my *working* VHDL
model of a SCSI host, used for exercising our SCSI disk controller IC interfaces in
simulation. He got confused by the active-low signals on the SCSI bus, so he added an
inversion to each signal. Then it didn't work any more, of course, so he added
*another* inversion to each signal.
After we convinced him to go work for somebody else (hopefully a competitor), we literally
rolled back his year of work in the revision control system. Sad, really. He was a nice
guy and he interviewed well, but he couldn't actually do anything productive in the
field we were working in.
--
Mark J. Blair, NF6X <nf6x at nf6x.net>
http://www.nf6x.net/