12 Dec
2001
12 Dec
'01
5:21 p.m.
On Wed, 12 Dec 2001, Pat Finnegan wrote:
On Wed, 12 Dec 2001, Boatman on the River of Suck
wrote:
What I was planning on doing is doing a custom set of bridge sets to talk
to multiple UNIBUSses (way multiple) simultaneously by way of a
channelized I/O system transparent to the software. (We are talking
multiple years of work).
Peace... Sridhar
On Wed, 12 Dec 2001, Jeffrey S. Sharp wrote:
And exactly how would you speak to UNIBUS?
Peace... SRidhar
How would you talk to unibus without the 300 or more wait states that
would make the 1G processor speed useless anyways? Unless you can hook
real IO devices up to the processor that are of *reasonable* speed, all
you have is a 'souped up adding machine' (to quote _Colossus:_
_The_Forbin_Project) Blatent
easy way out is emulate that 11/70 on athlon XP 1900+. :-)
Smack me if you dare. :-)
That would probably be his cheapest way to attain the speed he wants.
<ducks>