PDP-8 on FPGA project & where is Hans Pufal?

On 19/12/2008 15:53, der Mouse wrote: They're not quite the same thing, though a D-type flip-flop is a kind of latch. There are other types of flip-flops, such as T, RS, and JK types, usually edge-triggered. In a D-type, the active clock edge causes the output to change to match the input, and having changed, it stays that way, even if the input changes while the clock is still at the same level. The transparent latches that are commonly just referred to as "latches" (eg in data books, where you'll find some devices referred to as latches and others as flip-flops to distinguish them) are level-sensitive, and the output tracks the input (including changes) while the clock is at its active level. -- Pete Peter Turnbull Network Manager University of York