14 Jan
2011
14 Jan
'11
6:11 a.m.
On 13/01/11 21:29, Tony Duell wrote:
Not really... other than "read data is a 1us pulse every time there's a
transition" and similar stuff like that.
It's the minutiae that cause the trouble.
Hmm, fair enough. Doing it that way gets rid of a 555 timer, or a binary
counter on the CPLD and a 32kHz crystal oscillator.
Is there a
defined standard as to when the READY output on a
Shugart-type disc drive should go active?
Not that I a maware of. Are there any standards for anything on that
interface :-) Then I started
wondering... am I over-engineering this? Would waiting
for a couple of full disc rotations be enough to reliably generate a
READY signal?
I think that's massively over-engineered :-). Most drives just waited for
a couple of index pulses after motor-on which was enough time for the
thing to get up to speed. That is nto too suprising. Amstrad may have done a lot
of odd things, but
these drives did turn at 300 rpm and use the standard data rate.
Never a bad thing :)
I asusme you've looked at some old drive
schematics. The write circuit is
normally pretty simple, a divide-by-2 D-type clocked from the WD signal
and reset by WG (to get a consistent starring phase when writing),
That's the easy part :)
a couple of traisnstors to drive the heads and a
current sink. And a
bit of
enable logic. Often the transistors were part of a
tranistor array chip.
Hm, I don't think I have any discrete transistor array chips (unless the
ULN2003 and 2803 High Current Darlington Arrays count).. and the only
transistors I have any great number of are BC857s (BC547s in SOT23
surface mount packages).
The problem I'm trying to figure out is: how much current do I need to
put through the head, and how much current did the Amstrad board put
through it?
I'd rather like to avoid overloading the head -- permanently magnetising
or frying it would not be a good start.
Thanks,
--
Phil.
classiccmp at philpem.me.uk
http://www.philpem.me.uk/