31 Aug
2005
31 Aug
'05
1:55 p.m.
"Dwight K. Elvey" wrote:
>From: "Brad Parker" <brad at
heeltoe.com>
>
>Anyone recognize a line of "delay line" chips with names like TD25,
>TD50, TD100, etc... The look they were expensive at the time, like $10
>around 1976.
>
...
I would assume that in verilog, it was just a # delay.
The various taps delay events at the input by the specified
amounts.
heh. I guess I guessed correctly for the TD250 :-)
always @(posedge INPUT)
begin
O_50ns <= #(50) 1;
O_100ns <= #(100) 1;
O_150ns <= #(150) 1;
O_200ns <= #(200) 1;
O_250ns <= #(250) 1;
end
always @(negedge INPUT)
begin
O_50ns <= #(50) 0;
O_100ns <= #(100) 0;
O_150ns <= #(150) 0;
O_200ns <= #(200) 0;
O_250ns <= #(250) 0;
end