Tony Duell wrote:
Quite likely, although the control signals look unconventional. I would
It turns out it's write-while-read ram (no doubt you've caught up on your
email by now and read the pdf which was posted).
The strobe signal clocks the ram data into a latch. This is available
for some time, even if you do a write.
What device uses this RAM, and what are the control
pins conencted to?
It's used in the MIT CADR lisp machine, for the m-memory, which is a
high speed scratch pad used by the microcode.
I wrote some programs to convert the original CAD files (in SUDS) into
verilog and I've been (slowly) working on getting them to simulate. I
want to boot one under simulation and eventually put one in a simple
fpga (hah, by the time I'm 75 at this rate). I figure they'll make nice
christmas gifts :-)
I've got it fetching microcode from the prom. Most of the problems have
been with 74 style 'parts' I have made - in some cases I had to guess
because I have no data sheet but I'm slowly fixing that.
Also iverilog and cver both seem to have some small issues but mostly
work. I've used modelsim too but I perfer to run on linux.
-brad