17 Jun
2008
17 Jun
'08
9:09 a.m.
Allison wrote:
Have you ever used 8"SSSD to do anything that required space? There
isn't
enough space to run a disassembled version of the BDOS through ASM
unless you have at least two drives and don't mind doing cleanup.
I never could run the CP/M system I was using for more than 30 minutes
with out
the floppy stepper sticking. That was fun working with it. Still how do
you transfer
stuff from a floppy ( or file online ) to a CP/M system with no
external I/O devices?
Yes you can roll your own data sep it only needs three
ttl packages.
With all the other hardware needed for the 765 case you end up with at
least 10 chips
though If you willing to miss a few features it's been done in 7 plus
the FDC
and that doesn't include the bus side of the FDC interface.
That I would like to see.
Kicad for linux there are other like cadstd for winders.
Of course the last 2901 design I'd done in the early 80s was
with paper and pen! It's doable that way.
I still am using paper & pen.
Mind you I have to buy JAPANESE pens
since the quality of the USA stuff is all cheap Chinese imports.
Now that I have a serious cad program - DIPTRACE on order
I think I will put the design in hardware.
FYI using 250nS eproms will make it terminally slow
unless
you do two things, use a wide microword 64bits or more and
pipeline the address and decode so you can work right to the
eprom Tacc minimum limit.
I got that covered if I read the 2901 data sheets
correctly.
I will be using a 6809 style memory cycle optimized for
D-RAM access and clock the 2901 in 4th phase of
the memory cycle. This is retro computing project for the feel
of the late 1970's not using a 8 bit CPU. I am aming for
a 800ns memory cycle and the slow access of micro-code
is not a problem. The only thing pipelined is the next memory
cycle - Read/Write/Refesh and the default is refresh while
doing the the 1st cycle of op-code decoding. The front
panel does RUN/STOP, Single Instruction,Address Load,
Deposit,Read.