17 Jun
2011
17 Jun
'11
8:07 p.m.
On Fri, Jun 17, 2011 at 6:55 PM, Chuck Guzis <cclist at sydex.com> wrote:
On 17 Jun 2011 at 15:21, Dan Roganti wrote:
I guess a basic way to describe is Negative Logic design is using a
different frame of reference.
Maybe a good analogy is whether you use RPN or alebra for your math.
Whether you're using TTL or ECL, the voltage levels are relative.
With Positive Logic, the True state, Logic 1 is a positive voltage relative
to the off state.
With Negative Logic, the Tru state, Logic 0 is a positive voltage relative
to the off state.
So in the case of ECL, with a Vee of -5.2v the off state is -0.8v which is
more positive than -1.8v
I hope you don't expect all databooks past
& present to be revised :)
These were always written in the context of positive logic.
No, but I do expect the knucklehead drawing the schematic to use the
symbol that best describes the function of the gate.
I'm still not following you--if you're referring to voltage levels
being positive or negative, e.g. ECL, I still consider that to be
positive logic (as expressed in the databooks), even though both
logic 1 and 0 are more negative that 0V, but 1 is more positive than
0. But that's just a convention.
If you're talking about designing in DeMorgan equivalents, I don't
see the issue, unless one is unpracticed. One should be as natural
as the other--looking at a truth table, one should see it in both
senses.
I guess another basic way to describe is this way
A positive Logic AND gate is the equivalent to a Negative Logic OR gate.
It's not the bubble input/output OR gate that you see when using DeMorgan
theorem..
So the true state in a AND gate is inverted when you're using the OR gate.
Another example is the SR latch
These days you typically see the NAND gate SR latch.
Where the Q output is set to True state(logic1) using the low input - assert
logic O
This is still postive logic , but with inverted assertion level on the
inputs
Before when the first IC's came about 50yrs ago, you typically see NOR gate
SR latches.
Where the Q output is set to True state(logic 0) using a True state/low
input - logic 0 again
So the NOR SR latch is really a Negative Logic SR latch
A very good example of Negative Logic design is the NASA AGC.
.
.
.
On the other hand, conventional logic symbols are weak in that they
shows the component units, but doesn't necessarily show what they're
supposed to do. For example, it may be expeditious to construct a
XOR gate from leftover NAND gates and inverters, but there's no good
way to show the intended function and still keep the components
identified.
you can actually build a XOR gate from only just 4 NAND gates
I hope my skills in ascii schematics are still good (using courier font)
+-----\
+--------------------| \
| | O---+
A input | +-----\ +-----| / | +-----\
----+---| \ | +-----/ +-----| \
| O--| | O--> output
----+---| / | +-----\ +-----| /
B input | +-----/ +-----| \ | +-----/
| | O---+
+--------------------| /
+-----/
=Dan