24 Jul
2006
24 Jul
'06
2:02 a.m.
Chuck Guzis wrote:
On 7/23/2006 at 11:52 PM woodelf wrote:
You didn't mention how "vintage" your
ALU is going to be (I'm assuming this
is a vintage design and not an FPGA). Are you using something like the
74S481 4-bit slice or are you going for something from the 29xx family?
I was planning to use generic 2901's and LS parts other than PROM.
Ripple carry for the ALU is used since this is only 5 slices. Since I am
using a 6809 style clock I hope to get about 1.5 Mhz with the system
with a non-pipelined ROM.
Cheers,
Chuck