-----Original Message-----
From: cctalk [mailto:cctalk-bounces at
classiccmp.org] On Behalf Of Camiel
Vanderhoeven
Sent: 12 July 2016 09:56
To: General Discussion: On-Topic and Off-Topic Posts
<cctalk at classiccmp.org>
Subject: RE: IBM 360/30 in verilog
Op 12 jul. 2016 10:14 a.m. schreef "Dave Wade" <dave.g4ugm at
gmail.com>:
> -----Original Message-----
> From: cctalk [mailto:cctalk-bounces at
classiccmp.org] On Behalf Of
> Curious Marc
> Sent: 12 July 2016 08:58
> To: General Discussion: On-Topic and Off-Topic Posts
> <cctalk at classiccmp.org>
> Subject: Re: IBM 360/30 in verilog
>
> Darn. My hopes are shattered. Lots of Verilog in my future, that is
> if
we
can
find 360/50 ALDs...
Marc
It actually might be easier to produce a generic S/360 clone in FPGA
using the POP rather than individual ALU's.
Having built a very simple CPU (in VHDL not Verilog) and planning to
start on a more complex (Ferranti Pegasus) Of course it wouldn't be
cycle accurate, but perhaps that wouldn't be important.
Sure, a generic one would be simpler, but the point of doing an accurate one
of a specific model (65 in my case) is to accurately drive the panel that shows
the internal registers and opening of gates.
I think you are correct. I had assumed that the panel only displayed the normal 360
registers, in which case
the VHDL could easily route these to a panel, but on reading the 360/65 Functional
Characteristics
I can see several registers are displayed that are not mentioned or defined elsewhere so
you would need a
Set of ALDs for the 65 (or possibly a 67 as that?s basically the same machine) to get a
full panel display. It would
Also be nice to see what is on the roller selector switchs as that page in the manual has
not scanned very well..