On 10/27/2017 12:06 PM, Paul Koning via cctalk wrote:
But that doesn't directly relate to gate level
emulation. If you
have gate level documentation you can of course build a copy of the
machine out of actual gate-type parts, like 7400 chips. Or you can
write a gate level model in VHDL, which is not the most popular form
but certainly perfectly straightforward. Either way, though, you
have to start with a document that shows what the gates are in the
original and how they connect. And to get it to work, you need to
deal with timing issues and logic abuse, if present. In the 6600,
both are very present and very critical. For example, I've been
debugging a section (the central processor branch logic) where the
behavior changes quite substantially depending on whether you favor S
or R in an R/S flop, i.e., if both are asserted at the same time, who
wins? And the circuit and wire delays matter, down to the
few-nanosecond level.
This. In particular, google for a shot of the 6600 backplane. Many of
those twisted wires were cut to provide specific delays. Remember the
nanosecond-foot? A lot of the old hardware used this in the design.
I've long had a fantasy about building a core-logic CPU such as the
Univac Solid State. But heck if I know where one would get the "hard"
magnetic cores today. Another example of something you can't do with
commodity TTL.
--Chuck