Which Dec Emulation is the MOST useful and Versatile?

But that doesn't directly relate to gate level emulation. If you have gate level documentation you can of course build a copy of the machine out of actual gate-type parts, like 7400 chips. Or you can write a gate level model in VHDL, which is not the most popular form but certainly perfectly straightforward. Either way, though, you have to start with a document that shows what the gates are in the original and how they connect. And to get it to work, you need to deal with timing issues and logic abuse, if present. In the 6600, both are very present and very critical. For example, I've been debugging a section (the central processor branch logic) where the behavior changes quite substantially depending on whether you favor S or R in an R/S flop, i.e., if both are asserted at the same time, who wins? And the circuit and wire delays matter, down to the few-nanosecond level.