20 Jun
2007
20 Jun
'07
12:32 p.m.
On Wed, 20 Jun 2007, Allison wrote:
It's an easy cpu to interface and use. One of
it's features is
that at reset the bus can be configured for 8 or 16 bit wide path,
for standard or varible microcycle and static memory or
Dram(with refresh).
However, it's not without its obnoxious bits.
On the T-11, all writes are performed as read-modify-writes. This is
annoying when interfacing to chips such as the HDC9224 (the disk
controller used in the RQDX3). In that chip, you access many registers
through a single port address; another port indicates which of the
registers is being addressed. The internal address port increments on
either a read or a write. This means that a naive interface to the
HDC9224 from a T-11 A) increments the internal address register twice
and B) can't write register 0 because the internal address register is
incremented during the read.
IIRC, they handled this in the RQDX3 by placing the 9224 in two separate
address regions; one ignored reads, preventing them from getting to the
9224.
--
roger ivie
rivie at ridgenet.net