14 Nov
2007
14 Nov
'07
7:43 p.m.
On Nov 14, 2007, at 12:48 PM, Eric J Korpela wrote:
Not that it matters that much anyway since a modern
processor on
non-trivial code is spending 90% of its cycles waiting for memory.
A few thousand cycles for an interrupt is nothing...
This isn't the case with some architectures. Intel's
HyperThreading is designed to address this problem, but it is broken
in its current implementation. Sun's Niagara architecture
(UltraSPARC-T1 and -T2) deals with it successfully.
Ah, the good old days when processor and memory
operated at nearly the
same speed.
Those days are back, with modern architectures like UltraSPARC/
Niagara. It's very tasty stuff. Zoom!
-Dave
--
Dave McGuire
Port Charlotte, FL
Farewell Ophelia, 9/22/1991 - 7/25/2007