21 Jul
2021
21 Jul
'21
2:08 p.m.
On Jul 20, 2021, at 8:15 PM, Brent Hilpert via cctech
<cctech at classiccmp.org> wrote:
...
The development of 3-wire topologies over 4-wire would have helped automation, or reduced
manual effort, considerably. For stringing, the really awkward aspect of the original
4-wire topology was the sense wire that angled through all the cores at 45 degrees to the
X,Y,I wires. This was alleviated in the 3-wire topology where there is just 90 degree and
parallel relations.
There is even such a thing as 2-wire core memory. That means no coincident current
addressing, instead each address wire directly addresses a column of cores and the sense
wires (horizontal) sense the bits in the word. CDC 6000 series ECS -- bulk core memory
used as a very fast block transfer storage -- was built that way, with 488 bit words (8
60-bit CPU words plus parity, 3.2 microsecond cycle time, 4-way interleaved to deliver a
CPU word every 100 ns CPU "minor cycle").
In the 1950s, bistable (square hysteresis loop) cores were used as logic elements. Ken
Olsen, the founder of DEC, did his MS thesis work on this. And I have somewhere an
article about a keyboard operated Morse code sending device from that era that is built
around a ferrite core shift register.
It isn't usually described this way, but a good way to think of conventional core
memory is as an array of logic elements. Each core is a three input AND gate, with the
inputs being X, Y, and not-Inhibit.
paul