On Dec 29, 2013, at 10:26 AM, Mark J. Blair <nf6x at nf6x.net> wrote:
On Dec 29, 2013, at 07:38 , Al Kossow <aek at bitsavers.org> wrote:
WHAT to use for the microprocessor and FPGA has
been the stumbling block for the 10 or so years of false
starts that I've had with microcontroller/FPGA projects. There never seems to be the
right way to glue the
two together.
I don't know whether you have particularly strong preferences for or against various
FPGA vendors. At work, we use Xilinx stuff heavily, including both bottom-end parts in the
sub-$30 range and top-end just-released OMFG-that's-expensive stuff. I tend to be
biased towards Xilinx FPGAs since they're what I have the most experience with.
<snip>
First I thought about using an open source 8051 core
that I read about, but at the moment I'm thinking of Xilinx's Microblaze core
family instead. I did a quick experiment and found that it took up around 25% of the
smallest Spartan 6 in the configuration I tried. Larger Microblaze configurations in other
Xilinx families can even run Linux.
There are also Xilinx parts that have hard ARM cores in them too.
To keep it ?classic?, I?m aware that one list member has done some work with a Xilinx
Spartan 3E and put a fairly complete PDP-11 as the programmable controller. That
implementation as I recall took only about 10% of the gate count in the 3E (I think it was
a 1200 but can?t be sure).
I?ve looked at this issue a number of times and I feel Al?s pain trying to interface an
FPGA to a micro. I?ve come to the conclusion that the best way to do this is to get some
open implementation of a processor and include it within the FPGA itself. That way the
interface between the micro and the rest of the logic can be exactly what you need/want.
Of course it means that there?s more stuff to implement in the FPGA. However, most folks
I?ve talked to, have found that the constraints with FPGAs is I/Os and not gate count.
TTFN - Guy