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On Nov 15, 21:40, Iggy Drougge wrote: registers... Yeah. Right :-) Someone decided that they'd not need more memory in the foreseeable future than could be addressed in 26 bits (where have we seen this reasoning before, I wonder) and in fact RISC OS even divided that into two images, logical and physical memory. The other part of the reasoning ws that you have to put the processor flags somewhere, and putting six bits in a 32-bit register is wasteful, and we only have sixteen registers to begin with, and we don't need all the width of the PC, and .. and... Anyway, that's how it came about, and RISC OS has always been restricted to 26-bit address ARM chips. Hence the recent discussions on comp.sys.acorn.* about why it would be too much work to make RISC OS run on the newst incarnation of StrongARM, which has a 32-bit mode but not 26-bit. I *think* the original StrongARM has both, but I could be wrong. Earlier ARMs (Arm2, Arm3, Arm{6,7,8}00 are all 26-bit address (No, I don't know how the memory management deals with the 256MB possible in a RISC PC; it came after I left Acorn). In fact, if you want to be pedantic, the PC itself is only 24-bit, because the bottom two bits of the register are flags used to indicate the processor mode (user, interrupt, fast interrupt, supervisor). The bottom two bits of the address bus are alway forced to zero, and all memory accesses are word-aligned. So how does it read a byte (or half-word) off an non-aligned address? Easy, it uses it's barrel shifter to rotate the word while loading! -- Pete Peter Turnbull Dept. of Computer Science University of York