23 Oct
2011
23 Oct
'11
3:01 p.m.
On Oct 23, 2011, at 3:17 PM, Tony Duell wrote:
And then there are the FPGA designers who design like
this : THey'll
enter a scheamtic in the schematic capture program and simulate it. It
doens't work so they say things like 'let's invert that signal and see if
that helps. OK, it didn't, what happes if we change that AND to an OR?'
No real method, no logic to what they are doing. I've met them...
Oh lord, and then there's the ones who make a pipelined structure, but can't be
bothered to figure out when a timing-sensitive signal is actually supposed to happen, so
they just make a giant delay chain or five and simulate until they've picked the
"right" bit position in the chain that simulates kinda-sorta right... And then
they don't even leave a comment in the HDL about what their ugly hack is even supposed
to do.
One of our customers actually had a number of VHDL files (about 2500 lines each) whose
headers indicated that they were co-authored by one Jose Cuervo, which seemed about right
given the contents.
And going back to circuit design, let's not forget the folks who put zener ESD
protection on everything, including the input ferrite beads! It was a circuit for a
military device - the kind used for landing planes on carriers - that I saw that on.
Designed by someone who makes twice as much as me and had been at the job for three or
four times as long.
- Dave