26 Aug
2014
26 Aug
'14
3:14 p.m.
On Tue, Aug 26, 2014 at 3:38 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
The Altair 4K mem board schematic indicates it puts
data on the bus when the board is addressed and MEMR asserted. It appears to ignore DBIN.
Is that schematic online? My cursory search turned up only a copy of
the manual without schematic.
Depending on the semantics one wishes to apply, rather
than having something extend the mem cycle as you suggest, it appears the front panel is
relying on a 'degenerate' mem board design that ignores DBIN.
Interesting.
(Of course calling it degenerate is hindsight, as it
was was the earliest S100 design.)
[stated earlier:]
We have to keep in mind that the first Altair was
something of a seat-of-the-pants design,
Of course. Having something that worked at all was quite an
accomplishment at that time. It's not surprising that it wasn't as
elegant as we might hope for with the benefit of hindsight. It also
had to be as inexpensive as possible, so if there was a kludge to get
the data bus for the front panel stable without adding a latch (and
perhaps even by *omitting* a gate that one might otherwise design in),
that would undoubtedly have been viewed quite favorably by the
designers.
Thanks for posting your analysis.