5 Dec
2007
5 Dec
'07
1:49 p.m.
On 5 Dec 2007 at 14:29, woodelf wrote:
I see active low press.
1 8 input nand gate to generate a high clock
to all the D F/F with '0' as input. The active low press sets the FF.
Reset is left for power on clear of the FF's.
So 1 8 input NAND and 4 dual FF's are needed.
My point was that there are many unanswered questions. Two keys down
at the same time would set two FFs, for example. If two keys are
down and one must decide, which gets priority? The first key
pressed, or the last key released? Is debouncing part of this
circuit? Since the "none pressed" never occurs after the first
keypress, is there an initial state?
Isn't this what engineering is about--to define one's requirements--
and then develop a solution?
Or am I just a geezer and too old-school?
Cheers,
Chuck