In a message dated 98-04-23 19:19:31 EDT, you write:
<< At 12:53 4/23/98 -0700, you wrote:
>Anyone want to buy an Osborne 1 for $1000? Didn't think so. However, if
>you're interested in trying to talk this guy down to reality, I have the
>contact info.
One of the original demo/proto Oz Ones with a metal case (of which Gale
Rhoades once said there were about a dozen) went for $1000 -- IIRC -- on
Onsale a couple of years ago. Not an ordinary one, no, but we have to be
sure what the dude's got.
__________________________________________
Kip Crosby engine(a)chac.org
http://www.chac.org/index.html
Computer History Association of California
>>
well, let's get the guy's email address. i'm willing to antagonize him about
the overhyped price, anyone else? >8->
david
Anyone have any info on a NEC PC-6001A? It has what looks like a
cartdrige or expansion port on the side and 2 joystick ports on the
other side. Along the rear are printer, tape, audio out, rf out,
video out and a volume control. Looks like it has a place for an
optional RS-232 port but this one doesn't have it.
Any info on this machine would be welcome; cpu, os, etc. Also, if
someone knows the pin outs for the printer and tape ports, that would
be helpful too.
Thanks.
-----
David Williams - Computer Packrat
dlw(a)trailingedge.com
http://www.trailingedge.com
<> The PDP-11 architecture has only 7 GP registers (since you can't really
<> the PC for just anything) but that's good for the times, and they reall
<> are interchangable, so I'd be willing to argue that it wins on that.
<
<I'm glad somebody agrees with me on that! IMHO the concept of a GP
<register is a RISC sort of thing. And, Allison, if you think RISC
<should be register-rich, I claim the PDP11 was for its date, and
<certainly was compared to micros of the 1970s.
Compared to maybe 6800 or 6502, the 8080 had 4 16bit registers (bc, de,
hl, sp). The z80 added a second set and IX/IY. But that was only one
aspect.
On the instructions RISC systems of the time and even later didn't have
the addressing modes and often had a distinct register load and store
instruction. The best example of that difference was an ADD (R1),@(r2)+.
Now compare that to the DG Nova and it is of a stark difference.
Of all the micros in my collection, none are RISC save for the PDP-8 and
6502 which in my mind come close.
I have: 1802, SC/MP, 6800, 6809, NEC D78PG11, 8748/9, 8751, 8080/8085,
z80, z180, z280, z8002, z8001, 808x, 8018x, 80286, 80386, 80486 and the
micro version of minis 6100(pdp-8), 6120(PDP-8+EMA) TI9900, PDP11(T-11,
F11, J-11).
Now something with a MIPS chip, ARM, sparc or some such would be a great
addition of a real RISC processor.
<I don't like the "one instruction per cycle" definition of RISC - for a s
<what is a cycle? I prefer to think of RISC as an "every cycle is sacred"
<philosophy - you don't waste cycles. I'd try to get _memory cycles_ as o
<as the hardware permits them - on the 6502, for example, one per cycle (a
<almost manages it!), on 8080/Z80/PDP one every two or three cycles - but
<wouldn't make them all instruction fetches!
Again the -11 fails on that definition. Typical instruction are several
clocks per cycle and several cycles per instruction. Now the Z280
approaches that at the bus level as it has a internal cache and pipline
but, the instruction set is non-risc.
<Except the early ones. Allison, are you sure it was the 11/05? I claim
<it was the 11/15 (I have an 05). However I will concede that 05 may
<have at one time been a name for an 11/20 variant.
It may have been the 15.
I'm not saying RISC is bad only that the PDP-11 is not RISC.
Allison
OK, Now I can make myself an rsx11m.sys, VMR is, BOOt it, but when I say
SAV, it runs for awhile, types "CAN'T FIND HOME BLOCK", and halts.
It also complains about having to reduce partitions to the soze of the
common area (?), and the TT: driver is bigger than 4K.
What've I done? I just switched DY and DL in the sysvmr.cmd file,
and removed DU (The driver is corrupted...)
-------
[PDP11 risc or cisc]
Pete Turnbull:
> I know that was directed at Allison, but I'd say that key features of RISC
> architectures include large numbers of general registers,
> one-instruction-per-cycle, and hardware decode rather than microcode, not
> just the obvious minimised instruction set.
>
> The PDP-11 architecture has only 7 GP registers (since you can't really use
> the PC for just anything) but that's good for the times, and they really
> are interchangable, so I'd be willing to argue that it wins on that.
I'm glad somebody agrees with me on that! IMHO the concept of a GP
register is a RISC sort of thing. And, Allison, if you think RISC
should be register-rich, I claim the PDP11 was for its date, and
certainly was compared to micros of the 1970s.
> It loses on the one-instruction-per-cycle, though. Instructions take vastly
> different amounts of time to execute, depending on what they are, and
> they're all several cycles long. Just think about the FP instructions, or
Yeeeeesss...
I don't like the "one instruction per cycle" definition of RISC - for a start,
what is a cycle? I prefer to think of RISC as an "every cycle is sacred"
philosophy - you don't waste cycles. I'd try to get _memory cycles_ as often
as the hardware permits them - on the 6502, for example, one per cycle (and it
almost manages it!), on 8080/Z80/PDP one every two or three cycles - but I
wouldn't make them all instruction fetches!
> the Commercial Instruction Set. That's not the most CISC thing you've ever
> seen? :-) At a more mundane level, the additions of instructions like ASH
Despite having a 11/44, I have never seen a Commercial instruction Set :-)
> is pretty CISC -- in fact the whole idea of extending the instruction set by
> altering or adding to microcode is the essence of CISC, and the antithesis
> of a Reduced Instruction Set Computer.
Agreed. Later PDPs were more CISC, and this reached its maximum in the
Vax. But the basic architecture is IMHO a risc one - very simple and
very powerful.
> And of course it loses on the microcode vs hardware decode.
Except the early ones. Allison, are you sure it was the 11/05? I claim
it was the 11/15 (I have an 05). However I will concede that 05 may
have at one time been a name for an 11/20 variant.
> Similar, but in many ways quite different. I just had this argument (from
> a somewhat different point of view) on another mailing list. The 68K is
> much more like a PDP-11 than anything else, but it has a lot of clutter
> added.
Fair enough.
> That's my third of a tanner.
:-)
Philip.
PS I shall try and refrain from further comment on this issue - I don't
want to be the one who started a RISC versus CISC flame war!
<The PDP-11 architecture has only 7 GP registers (since you can't really u
<the PC for just anything) but that's good for the times, and they really
Really, you can do things to the PC that most micros don't even have
instructions for. there are four addressing modes of not for the PC
immediate, absolute, relative and relative defered which when applied
to a any other register are autoincrement, autoincrement defered,
indexed and indexed defered. That distinction is quite powerful and
only some of that is available in many micros and generally distinct
instructions. Most micros have a data follows instruction (immediate)
and an address follows instruction (absolute) but the other two are
far less commonly implemented.
The biggest non-risc is the addressing modes some are impossible for most
risc machines. The two operand addresses uncommon to RISC and most
micros. Add to it the defered mode (register contains the address of
a word in ram that contains the address of an operand). That impacts
compiler complexity and code density.
<And of course it loses on the microcode vs hardware decode.
Oops. The chip versions are microcoded as was the 11/60 but I believe
the 11/05 and 11/20 were hardware decode.
Allison
><>fits in the primary cache of an Alpha. If possible, you'd be using the
><Alpha
><>essentially as a programmable microengine and programming it to be
><PDP-11.
><>The reason to fit it in the primary cache is because of how the Alpha
><boots;
>
>Huh? a PDP11 emulator for alpha would be written as PAL to get the best
>results. Caching it is pointless as it's still a 16bit machine and
>would still flog itself to death trying to manage a data file greater
>than fits in ram (4mb max on PDP11 and some of that would be code!).
You misunderstand. I'm not talking about caching any PDP-11 code or data,
just the Alpha code which executes the emulator. Any memory fetch which
fetches Alpha code is overhead; a real PDP-11 wouldn't have to make that
memory fetch. If you can build a PDP-11 emulator small enough to fit in the
primary cache, all of your memory fetches can be payload.
It wouldn't really be PAL code because it would be executing in the chip's
boot environment; loaded from SROM into primary cache and staying there.
It owuld have a lot of the characteristics of PALcode; the extra registers
which Palcode depends upon would be visible, the MMU would be off, etc., but
it wouldn't really be PALcode because it wouldn't be called by a PAL trap.
Roger Ivie
ivie(a)cc.usu.edu
> Competing against the mostly 16bit 8088/6 and the 286 the PDP11 was out
> front. To match a 16bit cpu against a 32bitter... you must be inhaling!
FWIW, it's been my experience that on problems small enough to be tackled
by the J-11, an 18MHz J-11 eats the VAX-11/780 for lunch.
Roger Ivie
ivie(a)cc.usu.edu
Can anyone here help them out? Please respond to them and not me.
Thanks.
-----
Date sent: Thu, 23 Apr 1998 14:37:31 -0400
From: Liz Huntley <lizh(a)cannet.com>
Subject: Laser, Pal286
A question if don't you mind?
I'm tinkering with a Laser, Pal286. A customer of mine uses it, it had
a HDD Controller Failure. It actually works pretty well when it's
working. I don't suppose you know where I could get a working
motherboard for it... which I'm guessing that it needs.
I appreciate any info.
Thanks, Liz Huntley
| o_ | \ _ _ o _ ._ _ Liz Huntley
|_|/_ |_/(/__> |(_|| |_> lizh(a)cannet.com
_| Canton, Ohio
-----
David Williams - Computer Packrat
dlw(a)trailingedge.com
http://www.trailingedge.com
On Apr 23, 13:14, Philip.Belben(a)powertech.co.uk wrote:
> First, thanks to Pete, Allison and others for explaining the PDP11-23
> stuff. I stand corrected, I suppose.
I just like to show off :-)
> A long running discussion. Allison, I don't understand how you can say
> that the PDP11, with its very simple instruction set, is _more_ CISC
> than (say) the 80286, with which you compare it here. To my mind the
> only really CISC feature of the PDP11 is the MARK instruction. I fear
> we may be talking at cross purposes, and may mean different things by
> RISC and CISC - could you give some specific examples, please?
I know that was directed at Allison, but I'd say that key features of RISC
architectures include large numbers of general registers,
one-instruction-per-cycle, and hardware decode rather than microcode, not
just the obvious minimised instruction set.
The PDP-11 architecture has only 7 GP registers (since you can't really use
the PC for just anything) but that's good for the times, and they really
are interchangable, so I'd be willing to argue that it wins on that.
It loses on the one-instruction-per-cycle, though. Instructions take
vastly different amounts of time to execute, depending on what they are,
and they're all several cycles long. Just think about the FP instructions,
or the Commercial Instruction Set. That's not the most CISC thing you've
ever seen? :-) At a more mundane level, the additions of instructions
like ASH is pretty CISC -- in fact the whole idea of extending the
instruction set by altering or adding to microcode is the essence of CISC,
and the antithesis of a Reduced Instruction Set Computer.
And of course it loses on the microcode vs hardware decode.
> For those who think a souped up PDP11 could be a pentium killer, bear in
> mind that there was a 32 bit PDP11. I don't mean the VAX, and I don't
> mean the PDP11-68: I mean the Motorola 68000. AFAICT the two
> architectures are very, very similar. Is it a Pentium killer? The
> 68070 might have been but it's rather faded away now...
Similar, but in many ways quite different. I just had this argument (from
a somewhat different point of view) on another mailing list. The 68K is
much more like a PDP-11 than anything else, but it has a lot of clutter
added.
That's my third of a tanner.
--
Pete Peter Turnbull
Dept. of Computer Science
University of York
