> From: Paul Koning
> I wrote a simple program to strip off those two bytes everywhere, and
> the result was a set of V7 kit tapes that work nicely.
Any chance you could provide those 'ready to run' tape images back to
BitSavers, so other people don't have to replicate what you did?
> Trying to remember how to do a V7 installation with no docs was
> interesting...
Any chance you could write up some notes covering what your rememaber/did, for
anyone else who'd like to try running RSTS-11?
(I'd upload them to the Computer History wiki, if you like - I've, alas, not
had any luck getting in touch with the Webmaster there about getting other
people accounts...)
When did V7 come out, BTW?
And in looking around BitSavers a couple of days ago for RSTS-11 stuff, I
didn't think I found much in the way of sources, just the binaries. Did
I miss any?
It would be really nice to have sources - are they gone forever?
Noel
Gents,
I'm looking at a set of RSTS V7 magtape images (a release kit) which have an odd format that gives SIMH fits.
In the container formats I'm used to, each tape block image is preceded and followed by the data length as a 4-byte value. In SIMH that's rounded up to even, in E11 format it's not, but apart from that this is how things work.
The V7 tape images don't match that format. It looks like each block contains not just the data but also 2 more bytes, and the data length value represents that extra 2 bytes. So the tape label is 16 bytes, not 14, and the data blocks are 514 bytes, not 512.
Does this ring any bells? Where do those extra bytes come from? Can SIMH be told to deal with this or does it require a repair program to fix the format?
paul
(n.b.: Sorry for the "wanted" spam from me. I think this is the last
one for a while!)
I have access to a friend's AT&T 3B2 Model 400 for exploratory and
reverse-engineering work, but I would really like to get a system
of my own.
To that end, if you have an AT&T 3B2 you'd like to part with, please
drop me a line. Happy to pay fair market prices, or consider some
trades if you prefer that (I have a lot of DEC Qbus stuff)
I'm also still looking for more documentation. I especially wish I had
schematics, and any docs related to writing drivers. Anything that
would be useful in documenting the 3B2 internals would be lovely.
Thanks!
-Seth
I am currently rack-mounting my PDP8/e and its peripherals. And of course I want
to have the peripherals power up when I turn on the CPU. I have an 861 power
controller in the rack, but you can't just link that to the power
control sockets
on the CPU, DEC changed the wiring at some point...
Let me explain.
The 3 pin power control sockets on the 861 and just about every other power
controller and all my PDP11s carry the following 3 signals : Ground, On/ (ground
to turn the unit on) and Off/ (ground to force the unit off, e.g. for
an overheat
shutdown).
The 3 pin sockets on the PDP8/e CPU are not wired quite in parallel. One pin
is ground. Another pin is On/ (as above). But the middle pins are linked via the
frontpanel switch and overheat thermostat. The normal thing to do is to put
a jumper in each socket so that one side of the switch is grounded, the other
goes to On/. If you have more overheat thermostats in peripheral boxes, they
can be linked into the chain. There is a mains output on the PDP8/e PSU that
was (according to the printset) used to operate a contactor directly to power
up the peripherals.
A moment's thought made me realise you could use a normal power controller
with the PDP8/e. The only disadvantage is that the overheat switch in the
power controller would not shut down the CPU. Since I don't run my machines
unattended that is no great loss.
What I did was to cut a normal DEC power control cable (with the 3 pin plug
one each end) in half. Call the 2 halves 'CPU' and 'Pwr'
Then wire as follows :
CPU/Green (Gnd) - Pwr/Green (Gnd)
CPU/Red (On/) --->|--- CPU/Black (Switch)
Pwr/Red (On/) --->|--- CPU/Black (Switch)
Pwr/Black (Off/) : Not connected
Now plug the ends into the power controller and one of the CPU
power control sockets (make sure you have them the right way
round). In the other CPU power control socket fit the jumper plug
that links the middle pin to ground.
The idea is that when the CPU switch turns on, both the CPU On/
line and the power controller On/ line are pulled to ground via the
diodes. The diodes prevent the voltage from one power switching
circuit ending up in the other.
The diodes can be just about anything that will carry the power
relay coil current. I used 1N4007's as I happen to have them to
hand. I built it in a spare telephone junction box with 6 pairs of
terminals. One set of terminals carries the cables. The other
set carries the diodes and a wire between the 2 ground wires.
Needless to say construction is not critical. It's very low speed,
it's about 24V (and isolated from the mains) at < 1A.
-tony
I have a very nice SWTPC 6800 for sale. Please see the ad on the VCF
forums for complete information.
If you have inquiries, please do send them directly to me via e-mail.
Thanks!
Sellam
> From: Alfred M. Szmidt
> System 46 for the MIT CADR is licensed under a 3-clause BSD license --
> start hacking. ;-) You even have an emulator for the MIT CADR.
Everyone seems to have blown right past this, but it might be important.
Does anyone know if the Lambda matches the CADR? Or did they make changes
('improvements')? I always had the impression that it was basically a CADR
clone.
A CADR emulator, running the MIT code, would certainly be OK.
Noel
Hi folks,
Clear one problem and hit another is just what I expect to happen with this
Executel :)
After last weekend's little breakthrough my little machine is now hitting a
loop that LOOKS like it's waiting for an RST6.5 interrupt*, but at the same
time the A9 line is doing this:
http://www.binarydinosaurs.co.uk/STCExecutelOddTraceA9.jpg
(scale doubled for ease of viewing)
That doesn't look normal to me, but all 8 chips that touch A9 check out OK
and there's nothing odd resistance wise.
Before I start chasing my tail again I thought I'd ask first...
(*for anyone interested RST6.5 is triggered by the TS1/TS2 status lines from
the MR9735 teletext decoder and should be constantly active while video is
being output. At one point Tony suggested this chip needs to be initialised
and there is indeed a control word that can be passed to it to turn it on
and off which makes me wonder if there's another memory bit stuck somewhere)
Cheers!
--
Adrian/Witchy
Binary Dinosaurs creator/curator
Www.binarydinosaurs.co.uk - the UK's biggest private home computer
collection?