That is a very nice and robust part you linked to. Looks perfect
________________________________
From: Ethan Dicks <ethan.dicks at gmail.com>
Sent: Feb 14, 2017 10:03 AM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: New batch of pdp8 OMNIBUS to USB interface! Please Read and react!
On Tue, Feb 14, 2017 at 8:27 AM, Alfred M. Szmidt <ams at gnu.org> wrote:
> FWIW, Mini-B connectors are on their way out, nor USB OTG compliant.
> Though agreed that they are flimsy... Why not just a type A or
> something? Easy, big, and robust.
This is a peripheral. USB OTG doesn't apply, and USB-A would be
"inappropriate". Pretend this is an inkjet printer. What plug would
you expect to find on that?
I don't _mind_ Mini (I have a number of devices and cables that are
mini) and it _is_ more robust than Micro (I have seen plenty of phones
and tablets with broken micro plugs).
I have a suggestion... put 4 vias on 0.1" spacing next to the micro
connector so we could, for example, add a chassis-friendly exit cable
of our own purchase/manufacture if we choose, to have a nice fat USB-B
on the outside of the case.
https://newnex.com/images/UHR1-B-0005Blarge.jpg
-ethan
AT&T 3B2 Computer UNIX System V User Reference Manual
Original red hardcover, 3-ring binder, 9"x9"x2" Published July 1985
Excellent condition, never used
Best offer plus $10 for shipping.
Tony Duell wrote:
> My first thought, and it's probably wrong, is that these instrucitons
> (which differ by one bit, so might be
> setting/reseting something) are NOPs to the CPU, but are interpretted
> by the memory mapping hardware in those
> 9825s that have more than 64K or RAM and ROM total.
This seems likely. According to your schematics, gate U47 detects the pattern 0701xx. This signal feeds into the U43c flipflop, which appears to latch the state of the low 4 bits of the MAD bus into register U42, which sets the state of the /ForceRAM (bit 3), /ForceROM (bit 2), /DiagRd (bit 1) and ALLROM (bit 0) signals. Thus, these two instructions appear to toggle the state of the /ForceROM signal.
If I?ve wrapped my brain around the details it appears that 070113 deasserts the /ForceROM signal, and 070117 asserts it?
I agree quite a unique bit of code
On Feb 13, 2017 4:07 PM, "Noel Chiappa" <jnc at mercury.lcs.mit.edu> wrote:
> From: Tony Duell
> My first thought, and it's probably wrong
Apparently not... :-)
> these instrucitons (which differ by one bit, so might be
> setting/reseting something) are NOPs to the CPU, but are interpretted
> by the memory mapping hardware
Ooh, very clever/cool.
Noel
> From: Josh Dersch
> (while installing the MMU and Stack Limit Register in my own 11/40)
BTW, I think I found out why the MMU requires the SLR. The SLR is not
operative in User mode. I haven't checked out the circuitry to see exactly
what the interaction is, but it has to be something associated with that.
> you *will* need an LTC to run V6 UNIX
Actually, it will work with a KW11-P, too; those are actually more commmon
than the KW11-L's, I've found. But as Guy pointed out, the DL11-W will do too
- and those are _very_ common (since they were used in the 11/34's, etc).
Noel
> From: Tony Duell
> My first thought, and it's probably wrong
Apparently not... :-)
> these instrucitons (which differ by one bit, so might be
> setting/reseting something) are NOPs to the CPU, but are interpretted
> by the memory mapping hardware
Ooh, very clever/cool.
Noel
Looking for a DATAC 1000 if anyone has one for sale or trade (or a site
with pictures). This is a Philadelphia USA origin 6502 trainer. I am
interested in it for the local history.
Thanks
Bill
> From: William Degnan
> PDP 11 KE11E M7238 EIS board (for PDP 11/40) which causes the CPU to
> crash when installed; front panel not responsive
> ...
> I installed a removable jumper so I can flip jumper configs back and
> forth between EIS installed/not installed. Without the EIS the system
> works fine
To understand this symptom, one needs to understand how the EIS interacts
with the main CPU. Both include microcode, and what is supposed to happen is
that when an EIS instruction happens, control is passed to the microcode on
the EIS board (the actual microcode words being fed back to the main CPU
through those three over-the-back jumper cables). The microcode on the EIS
board can then control the data paths, etc in the main CPU, to feed the EIS
data, and take back the results of the computation performed on the EIS card.
I'm trying to understand what W1 does, but I'm not there yet. It's shown on
the KD11-A print K3-8 (pg. 48), in the lower left corner, but its effects are
somewhat obscure.
To start with, the array of odd chips E6-E7 (74H60's) and E17 (74H53) are
expandable AND-OR gates. I'd never seen these before, but the lines running
to and from pins 11 and 12 on the 'H53 join the other three gates below it
into it - i.e. that whole array of AND gates all feed into one NOR gate
(output on pin 8 of the 'H53).
So far, so good, but from there I'm still lost. When W1 is inserted (no EIS)
it grounds the signal ECIN00, which comes in from off-board (as shown by the
"A05S2", which is the pin it arrives on). The output of that giant NOR gate
is CIN00, which is immediately sent off-board (pin 'A05P1'). I have yet to
try and chase these signals down, and work out what they do; the KD11-A Tech
Manual is fairly cryptic on the subject.
Note also that, IIRC, the front console operates under control of microcode.
So I'm _guessing_ that what is happening is that somehow the EIS is, when
enabled, messing up the operation of the microcode in the main CPU, causing
it to freeze.
> Thought - I don't have a LW11L, M787 installed. ... Do you think that
> maybe the EIS board requires this for some reason
No. I've looked at the KW11-L prints in the past, and it's just a very simple
UNIBUS device. I don't see any way it not being there could cause the
symptoms under discussion.
> I could swap out the current 11/40 backplane with a backplane that has
> the jumpers for the M787 already removed
I think it's only one jumper - for BG6, no?
> I neglected to mention I had no M787
To run Unix V6 you'll need either a KW11-L or KW11-P (see previous
discussion about how Unix needs a clock - both at a low level, because
it will panic() if it doesn't find one, and at a high level, because
even if we patch the panic, stuff won't 'work right' without one).
Noel
Question - I am working on a PDP 11 KE11E M7238 EIS board (for PDP 11/40)
which causes the CPU to crash when installed; front panel not responsive,
can't boot XXDP. I installed a removable jumper so I can flip jumper
configs back and forth between EIS installed/not installed. Without the
EIS the system works fine, can boot OS's that do not require it like RT11.
As discussed before the EIS is required if I want to boot up UNIX 6 on the
11/40, which is a goal of mine.
Thought - I don't have a LW11L, M787 installed. This is a the Line TIme
Clock option card. Do you think that maybe the EIS board requires this for
some reason, even though there are no references to this as a requirement
in any docs I can find? Maybe the docs writers assume it's installed? I
only wonder because any time I have seen the M7238 installed in an 11/40 I
have also seen a M787.
I could swap out the current 11/40 backplane with a backplane that has the
jumpers for the M787 already removed, but I only want to do this if it's
necessary. When we were talking before I neglected to mention I had no
M787, you may have assumed I did.
Bill