On Tue, Jun 22, 2010 at 1:08 PM, Rob Jarratt
<robert.jarratt at ntlworld.com> wrote:
> I have a MicroVAX 3400. It uses quite a lot of power compared to my other
> MicroVAXen (about 180-200W). It has an M9060 Load Module installed and I
> understand that this is needed to give the power supplies enough load to
> work correctly. However, if I have enough stuff already in the machine then
> it would seem that this module is just sucking up power needlessly. How much
> stuff do you need in the machine to make the M9060 redundant?
>
> Incidentally, anyone know why this machine has two PSUs if they are not (as
> I have read somewhere) redundant?
The power planes of a BA213 backplane are split into a left half
(slots 7 to 12) and a right half (slots 1 to 6). Each power suppy
only supplies its half of the backplane. If you look at the bare
backplane there are power bus bars at the top and and bottom of the
slots which are visibly split into a left half and a right half.
The BA213 Enclosure Maintenance manual (EK-189AA-MG-001) says that a
M9060 load module must be installed in one of the backplane slots 7
through 12 if the continuous minimum current drawn on the second power
supply is less than 5 amperes. If the minimum current of 5 amperes is
not reached, the power supply enters an error mode and shuts down the
system.
I have a MicroVAX 3400. It uses quite a lot of power compared to my other
MicroVAXen (about 180-200W). It has an M9060 Load Module installed and I
understand that this is needed to give the power supplies enough load to
work correctly. However, if I have enough stuff already in the machine then
it would seem that this module is just sucking up power needlessly. How much
stuff do you need in the machine to make the M9060 redundant? At the moment
I have a KA640 CPU and a KA655 CPU, two 16MB memory boards a DESQA and the
TK70 controller. I do not yet have any DSSI disks for it, nor do I have a
KFQSA, but the KA640 has DSSI built in.
Incidentally, anyone know why this machine has two PSUs if they are not (as
I have read somewhere) redundant?
Regards
Rob
"Walter F.J. Mueller" <W.F.J.Mueller at gsi.de> wrote:
> Hi there,
>
> Brad Parker just posted about his FPGA implementation of a PDP-11,
> which boots so far RT-11, RSTS V4, BSD 2.9 and Unix V6. There was a
> question how fast an FPGA solution might be compared to a PDP-11/93.
>
> I've also implemented a PDP-11 on an FPGA. It is a full 11/70 with
> split I&D, MMU and cache. No FPP so far. Available peripherals are so
> far DL11, LP11, KW11L, PC11, and RK11. All I/O is channeled over via
> 'remote-register-interface' onto a single bi-directional byte stream
> interface, so the FPGA board needs a backend PC with a server program
> to handle the I/O requests.
Cool! Nice!
> The design is FPGA proven, runs on Digilent S3 and NEXYS2 boards, the
> former with 1 MB 10 ns SRAM, the later with 16 MB 70ns PSDRAM.
>
> Resource consumption is
> S3 board xc3s1000 2471 slices or 33%
> NEXYS2 board xc3s1200e 2624 slices or 30%
>
> The implementation was verified against many XXDP maindec's. There are
> some open issues, especially some details of trap and double error
> handling aren't correct yet. In practice this is of little importance,
> the FPGA system happily boots and runs BSD 2.11, a system using 22bit
> addressing and split I&D space. {Note: you need patch 447 for 2.11BSD
> to get FPP emulation and RK support working}
Any plans on the FPP? It would be really nice and useful to have.
As for traps and double errors, feel free to ask. I don't know if I have
all the answers, but I might be able to figure them out. Besides, I also
have access to one (or three) functional 11/70 machines.
> On Performance: The design runs at 50 MHz. I've run parts of the
> Byte Unix benchmark on the FPGA systems. Given that the FPP is only
> emulated by the 2.11BSD kernel it makes only sense to look at the integer
> benchmarks. The Dhrystone benchmark 'dhry2reg' gives about '11500 lps'
> on both boards. For comparison see Michael Schneiders page
> http://www.vaxcluster.de/mambo/bench2.php?mach=pdp11 which gives about
> '830 lps' for a 11/53. There is little Dhrystone difference between
> the two boards despite the very different memory access times. The
> 8 kB cache with 32 bit cache lines really helps on the NEXYS2 board.
The 11/53 is a really slow machine. Not that helpful to compare with.
But you seem to push a nice number anyway.
But 50MHz... The J11 in an 11/9x machine runs at 20 MHz, which would
suggest that you should only be able to push about 2.5 times the
performance, unless you do some more clever tricks.
(The 11/9x machine runs all memory as cache.)
> I'm in the middle of homogenizing some internal interfaces and of some
> code cleanup, also the backend handler needs a re-write in C++ (currently
> perl). When that's done I'll make the whole package (VHDL sources, test
> benches, backend) available on 'OpenCores'.
>
> Finally a comment to Dave Mitton's remark
>> > Now what would be really cool would be to make 4 CPUs and re-create
>> > an 11/74 quad.
>> > http://www.miim.com/faq/hardware/multipro.html#castor
*Sigh* I wonder if anyone is ever going to be able to set Bruce Mitchell
right on his facts.
CASTOR didn't disappear. I talked with Dave Carroll about it not so many
years ago, and the machine was still around, altough at that time with a
hardware problem causing it to be down.
(There are plenty of other small errors on Bruce Mitchells pages as
well, but from my small dealings with him in the past, he don't seem to
be interested in listening.)
> The reason why I picked a 11/70 and not a J11 as target is because my
> goal is a 11/74. I've implemented the IIST already and tested against
> the IIST Diagnostic I could find in XXDP (riiab0). A dual core will
> fit into a single xc3s1200e of the NEXYS2 board. The work needed is
> quite clear and doable (changes on cache, mmu, and cpu core for asrb).
> However, I've no plans to implement the CIS, so it will always be a
> subset of a 11/74. But for sure fun to do and run.
You do know that the J11 is already designed for mP usage, except that
DECs testing of that was even more secret than the 11/74?
The 11/74 definitely don't need CIS though. I don't think any prototype
11/74 even had it. It was planned for the next generation of the
machine, that never got built. Anyway, it was to be an option for the
CPU as far as I know. Just as FPP.
IIST is needed for RSX to be happy (the only OS that supports the
11/74), and you also need to implement parts of the memory bus behaviour
with interlocking. You can ignore the MK11 box CSRs, even though it will
look a little funny, but you do need separate DL11s for each CPU core,
along with the rest of the I/O bus, or else things will probably not
work. The 11/74 is a shared memory machine, but not shared I/O bus.
Johnny
Vintage Computer Festival comes to Chicago!
The fifth edition of VCF Midwest will take place in Chicago (OK, Lombard is
a suburb) this fall - join us on September 18 in conjunction with ECCC as we
once again coax vintage electrons into motion.
The show will run from 8:00 AM on Saturday on into the night, coming to an
official close at 1:00 AM Sunday morning. Early setup will be available on
Friday evening from 5-6:30 PM, at which time the exhibition area will be
locked until the show opens on Saturday morning.
In addition to exhibitions of eclectic electronica, we will feature
speakers, vendors and a Vince Briel workshop (come ready to homebrew!).
Admission is FREE to all whether you come to show, look, build, talk or
sell.
Exhibitor and session info to follow shortly, but save the date NOW!
Join us!
Jack Rubin
chiclassiccomp
Rooms are available at a reduced rate at the adjoining Fairfield Inn. Ask
for "ECCC" or "vintage computer" rates.
http://marriott.com/property/propertypage/CHIFS
Our Facebook Page -
http://www.facebook.com/event.php?eid=137065072974225
**************************************************************
Please feel free to share this information with others who might be
interested. Thank you.
PDP 8/L about 2 years ago at TRW. everyone was looking at it and
marveling at how old it was, and I was counting the 12 front panel
switches, and getting out my $1.
TRW (Northrup / Grumman, LA)swap meet has a combination of computer
users (like me with more than one PC in the house, and potentially a big
pile running), HAMs with their junk (sometimes bring in old computer
stuff), people dumping tailings from local DMRO (or whatever) sales, or
just scrappers with odd bits of stuff.
The computer scrap stores around are pretty much gone now, you have to
know the scrappers and deal with them. And I"m not talking about
"recyclers" though they might yield some things.
Jim
On 6/22/2010 12:05 AM, Rob Jarratt wrote:
> Would you say that a radio rally was a potential good source for computer
> equipment for someone who is not interested in radio, or were you just
> lucky? I have had a look to see what is on in my area and there is a radio
> rally coming up near me quite soon and I am wondering if it would be worth
> going along.
>
> Regards
>
> Rob
obtained 2 rainbows last night. The only k/b we could find in the guy's basement had a CTITOAH (or whatever the hell) designation, although it looked exactly like a R* k/b. I didn't argue the point. I now have 1 k/b between 3 R*s.
Haven't cracked the veep open yet. I imagine it has a z80 or something monotonous like that. I'll screech if it has an 8088/8086, but I truly doubt it. Text is blue, strange, but was told it's a mono monitor. Need anything anyone can provide for it. Thanks.
Wrong tools is sometimes just an excuse. I routinely solder SMD chips
with .025" pin spacing with a soldering iron with about a 3/32" tip.
Granted it is not my first choice, but my other iron died, and I'll use
what I have. Since it works, I don't have a lot of incentive to buy the
proper sized tip even though it makes soldering a LOT easier.
My first choice would be a Metcal with a proper sized tip!
And if I were in better shape financially and/or project wise, I'd take
the complete P112 kit just for the fun of soldering the SMD components
in place.
Marvin
>> The P112 looks pretty interesting. I'd consider a partial kit
>> depending on the price. While I have successfully soldered one SMT
>> part (the FTDI chip on the X0xb0x board), it wasn't fun and I would
>> probably like to try to avoid having to do it again. I think I just
>> lucked out that I didn't fry the chip. I bridged a number of pins
>> and had to clean up with solder wick.
>
> Wrong tools. Betcha anything.
>
> -Dave
Hi there,
Brad Parker just posted about his FPGA implementation of a PDP-11,
which boots so far RT-11, RSTS V4, BSD 2.9 and Unix V6. There was a
question how fast an FPGA solution might be compared to a PDP-11/93.
I've also implemented a PDP-11 on an FPGA. It is a full 11/70 with
split I&D, MMU and cache. No FPP so far. Available peripherals are so
far DL11, LP11, KW11L, PC11, and RK11. All I/O is channeled over via
'remote-register-interface' onto a single bi-directional byte stream
interface, so the FPGA board needs a backend PC with a server program
to handle the I/O requests.
The design is FPGA proven, runs on Digilent S3 and NEXYS2 boards, the
former with 1 MB 10 ns SRAM, the later with 16 MB 70ns PSDRAM.
Resource consumption is
S3 board xc3s1000 2471 slices or 33%
NEXYS2 board xc3s1200e 2624 slices or 30%
The implementation was verified against many XXDP maindec's. There are
some open issues, especially some details of trap and double error
handling aren't correct yet. In practice this is of little importance,
the FPGA system happily boots and runs BSD 2.11, a system using 22bit
addressing and split I&D space. {Note: you need patch 447 for 2.11BSD
to get FPP emulation and RK support working}
On Performance: The design runs at 50 MHz. I've run parts of the
Byte Unix benchmark on the FPGA systems. Given that the FPP is only
emulated by the 2.11BSD kernel it makes only sense to look at the integer
benchmarks. The Dhrystone benchmark 'dhry2reg' gives about '11500 lps'
on both boards. For comparison see Michael Schneiders page
http://www.vaxcluster.de/mambo/bench2.php?mach=pdp11 which gives about
'830 lps' for a 11/53. There is little Dhrystone difference between
the two boards despite the very different memory access times. The
8 kB cache with 32 bit cache lines really helps on the NEXYS2 board.
I'm in the middle of homogenizing some internal interfaces and of some
code cleanup, also the backend handler needs a re-write in C++ (currently
perl). When that's done I'll make the whole package (VHDL sources, test
benches, backend) available on 'OpenCores'.
Finally a comment to Dave Mitton's remark
> Now what would be really cool would be to make 4 CPUs and re-create
> an 11/74 quad.
> http://www.miim.com/faq/hardware/multipro.html#castor
The reason why I picked a 11/70 and not a J11 as target is because my
goal is a 11/74. I've implemented the IIST already and tested against
the IIST Diagnostic I could find in XXDP (riiab0). A dual core will
fit into a single xc3s1200e of the NEXYS2 board. The work needed is
quite clear and doable (changes on cache, mmu, and cpu core for asrb).
However, I've no plans to implement the CIS, so it will always be a
subset of a 11/74. But for sure fun to do and run.
With best regards, Walter
Heya. Given the penchant of people on this list to collect all sorts of obsolete and antique tech, I figured I'd throw a query out here.
I live in an old apartment block that has a 1920's vintage Western Electric intercom system. The system is in need of some "help" (it still works, but is far from what you'd consider 'optimal'). I'm a phone guy by trade, and would love to spend some of my personal time making this system work like it did when it was installed in 1927.
If anybody out there has any knowledge of antique intercom systems like this, please E-mail me off list. I can provide more information (like pictures of the equipment and a better description). Just don't want to further dive down this rabbit hole on this list.
For that matter, if there's a discussion list relevant to antique telephone systems, referring me there would be appreciated as well.