test-drb

test-drb@ccmp.vtda.org

101090 discussions

by tshoppa＠wmata.com

"Walter F.J. Mueller" <w.f.j.mueller at gsi.de> wrote: >> Johnny Billquist <bqt at softjar.se> wrote: >> > I wasn't aware that any prototypes ever were produced and came as >> > far as being functional. I thought it was just paper work that >> > had bee done. >> >> The 11/74 wasn't marketed, as pointed out in this thread, but a >> few systems were build by DEC. A picture of such 11/74 system >> was made available by Tim Shoppa, see >> >> http://www.trailing-edge.com/~shoppa/1174Xopen.jpg >> >> You'll nicely see the four CPUs. > Yes, I know of these systems. However, that is not an 11/74 on that > picture, but an 11/70mP. There is a difference... > As pointed out, the 11/70mP was marketed as an 11/74, but it's a > different CPU. > The easiest way to see that this is a picture of an 11/70mP is by > looking at the lower rotary switch, which only have four positions, and > not eight (which the 11/74 have). So no CIS on this machine. > The only 11/74 picture I've seen so far is the silk screen panel picture > posted a few days ago. Unfortunately I've already forgotten the name > (I'm lousy with names, sorry) of the person who posted it, and who also > worked on the 11/74 CIS microcode. > The machine on that picture is probably CASTOR:: by the way. The people who work with/maintain CASTOR:: call it a 11/74, FWIW. They never used the term "11/70mP" in front of me for sure. I would occasionally elicit comments about multiprocessing on 73's or 93's but it always came back to "our 11/74 does it THIS WAY" because that was the working example. I'm not saying that "11/70mP" is wrong, indeed it's used in some of the drawings and memos to describe what was commonly called the 11/74. CIS was real important to some DECcies circa late 70's for some Cobol requirement but coming from the real-time side none of us ever cared. We'd just run across machines that had this unneeded option. Tim.

15 years, 9 months

Ebay ISA NI AT-GPIB/TNT+. IEEE 488.2 (Analyzer), HPDrive compat?

by rdbrown＠pacific.net.au

Item number:300434169483 (9 boards @ USD10 + postage each) AT-GPIB/TNT+. IEEE 488.2 (ISA) Single-Board GPIB Interface and Analyzer I think the analyzer software that runs on Windows 95/98 and ME is bundled with the 1.70 version driver that may be available by request (from the 2nd URL) http://joule.ni.com/nidu/cds/view/p/id/532/lang/en http://www.ni.com/support/gpib/drivers/ I have run a similar card in a Compaq DeskPro 6500? P3 PCI machine with a legacy ISA slot (captured an HP150 boot sequence). As I read it the HPDrive software will run on Window 95/98, ME with this board. See the HPDrive site. http://www.hp9845.net/9845/projects/hpdrive/

15 years, 9 months

(OT) Laserjet III laser scanner module

by classiccmp＠philpem.me.uk

(... sending this from the correct FROM address would help...) Hi guys, I've got a Laserjet III laser scanner module kicking around in my junkbox, harvested from an utterly screwed LJ3. It has a fibre-optic light pipe on one side, which connects to a photosensor on the motherboard. Does anyone know what the frequency or period of the photocell signal is? That is to say, how long does it take for the scanner to make one complete pass from "horizontal blank" to the right margin -- in other words, the time from the leading edge of one photocell pulse to the next? I'm toying with the idea of repurposing the scanner module for another project (using a BluRay laser diode to print directly onto photographic paper then process using a 3-bath B&W process), and I'd like to figure out (in advance!) what the requirements will be placed on the paper drive system (among other things!) Thanks, -- Phil. classiccmp at philpem.me.uk http://www.philpem.me.uk/

15 years, 9 months

yet another pdp-11 in fgpa

by bqt＠softjar.se

"Walter F.J. Mueller" <w.f.j.mueller at gsi.de> wrote: > Johnny Billquist <bqt at softjar.se> wrote: > > I wasn't aware that any prototypes ever were produced and came as > > far as being functional. I thought it was just paper work that > > had bee done. > > The 11/74 wasn't marketed, as pointed out in this thread, but a > few systems were build by DEC. A picture of such 11/74 system > was made available by Tim Shoppa, see > > http://www.trailing-edge.com/~shoppa/1174Xopen.jpg > > You'll nicely see the four CPUs. Yes, I know of these systems. However, that is not an 11/74 on that picture, but an 11/70mP. There is a difference... As pointed out, the 11/70mP was marketed as an 11/74, but it's a different CPU. The easiest way to see that this is a picture of an 11/70mP is by looking at the lower rotary switch, which only have four positions, and not eight (which the 11/74 have). So no CIS on this machine. The only 11/74 picture I've seen so far is the silk screen panel picture posted a few days ago. Unfortunately I've already forgotten the name (I'm lousy with names, sorry) of the person who posted it, and who also worked on the 11/74 CIS microcode. The machine on that picture is probably CASTOR:: by the way. > arcarlini at iee.org wrote: > > I've read somewhere that it [PDP-11/74] was full of flat ribbon > > cables and would have been a beast to maintain. > > Well, you see on the picture that there was quite a bit of > flat ribbon cables :). Yes, when you run multiple CPU configurations, you do get many flat cables. However, if you were to run the 11/74 in a single CPU configuration, it would not have had more flat cables than an 11/70. So it seems strange if that would have been the reason for cancelling it. On the other hand, I think that CIS never was popular, or in any demand, for the PDP-11, so if that (and multiprocess capability) was the only things the 11/74 brought to the table to differ it from tne 11/70, then I can understand why they would cancel it if they had problems with the multiprocessor part. > The 'PDP 11/70 Multiprocessor Technical Manual (Preliminary Version)' > is on bitsavers, see > > http://www.bitsavers.org/pdf/dec/pdp11/1174/EK-70MP-TM_PRE_1170mp_Prelim_Te… > > and gives you a feeling of the modules and interconnects. Yes. And all evidence I ever see is that the only systems DEC actually did get working was the 11/70mP. That they actually got the 11/74 (CPU) beyond paperwork was what was news to me. > Johnny Billquist <bqt at softjar.se> wrote > > You do know that the J11 is already designed for mP usage, except that > > DECs testing of that was even more secret than the 11/74? > > Sure, the mP instructions WRTLCK and the TSTSET of the J11 are > documented, and allow cleaner way to implement spin locks than > the 'asrb hack' of the 11/74. In a future version of the w11a I'll > probably also implement the instructions supported by 11/34 and > J11 and make the 'processor profile' selectable at start time, much > like in the simh simulator. That would be nice. While RSX don't use it, you could use it for Unix, or other systems. The J11 also have the cache bypass bit in the PDR, btw. What instructions are you thinking about when you say 11/34 btw? > > But FPP is among the most important things in there as well, I'd say. > > Lots of software who won't be happy without it. > > That's true from a performance point of view. However > - you can run RSX and Fortran without FPP (did this 30 years ago > when the FPP broke on the 11/45 I was working with...). True. But you cannot run almost anything else. I don't think I've seen any other language that do not require the FPP. > - you can run 2.11BSD without FPP (I'm doing that each time I > boot 2.11BSD). Yes, that was fixed recently, right? > So a FPP is very good to have, but not my highest priority. Also, > it's quite a project to design, implement and verify it, with the > verification, as usual, being the most time consuming part. True. > > By the way. You don't have to worry about cache coherency. The > > PDP-11/74 do not do that. Cache coherency is managed by software > > on the PDP-11 (well, in RSX, since that's the only system that > > supports the hardware). In short, the real hardware do not implement > > any sort of cache coherency in hardware. > > I know, but I'll go for a cache with full cache coherency. That will > make it a lot easier to try a MP hack for 2.11BSD. And RSX, if I ever > get to it, will not mind. True. Definitely will not break anything. But it will make your life more complicated. :-) > Johnny Billquist <bqt at softjar.se> wrote: > > Good thinking. > > But I'm surprised by some numbers here. The J11 at 20 MHz is > > only slightly faster than an 11/70. In fact, if you can throw > > the 11/70 into running all from cache, it might even be slightly > > faster than an 11/9x. > > Or so I seem to remember from looking at the numbers back when > > I last was digging into this. > > > > Maybe I'm mixing some numbers up here... What I do remember for > > sure is that the 11/9x machines run at 20 MHz, and that they are > > not more than maybe 1.2 times the speed of an 11/70 in general. > > oops, you are right, I was mixing numbers here and forgot about > a factor of four. Here the revised arguments: > > See http://www.village.org/pdp11/faq.pages/prfmnc.html , there > is a table comparing 11/70 with various J11 systems: > > 11/23 11/53 11/73 11/83 11/93 > ----- ----- ----- ----- ----- > CPU F-11 J-11 J-11 J-11 J-11 > Microcycle(ns) 300 267 267 222 222 > Clock (MHz) ? 15 15 18 18 > Performance 0.2 0.5 0.7 1.2 1.4 > (11/70 = 1) > Cache no no yes yes no > Floating-Pt opt no no yes yes > Coprocessor > > My mistake was to forget that the J11 needs 4 clock cycles per > microcycle (MC), that's why 18 MHz clock leads to 222 ns MC period. > > In the end the J11 (222ns MC) is faster than the 11/70 (150 ns MC) > because it has a better micro architecture (three stage pipeline > vs. instruction prefetch only). The J11 is roughly a factor two > better compared to 11/70 in terms of MC efficiency. Hmm, I seem to remember checking numbers a while ago and came to the conclusion that if the 11/70 would have all memory as cache, it would outperform the J11. Atleast at 18MHz, maybe also 20MHz. (Btw, that table is slightly wrong, as the 11/9x eventually made it to 20MHz). I have a processor handbook which gives instruction speeds of 11/70 instructions with cache hits and without, which tells you how fast the machine would be if you were all cache. The 11/70 suffers because memory is so slow. Johnny

15 years, 9 months

yet another pdp-11 in fgpa

by w.f.j.mueller＠gsi.de

Johnny Billquist <bqt at softjar.se> wrote: >>.. >> "Walter F.J. Mueller" <w.f.j.mueller at gsi.de> wrote: >> At some later time maybe I'll try a really fast design, with separate >> instruction and data caches and significantly more parallelism than >> the J11 had. > Hmm. I wonder if that might cause headaches? There might be code out > there that require your i-cache and d-cache to be consistent with each > other. sure, there is self modifying code. The maindec zkdjb2 for example has a sequence like mov #000240,(pc) jmp (r1) and tests that the 'nop' was executed and not the 'jmp'. However, the cache, even separate i-d, is only one aspect, main point is to get all the different 'write-after-read' hazards in the pipeline under control. That's why I stayed with a simple 'prefetch-only' 11/70-like implementation in the first round. Even in that case one has to be careful and suppress for example the prefetch when the destination is pc. Otherwise a 'clr pc',often found at the end of primary bootstraps, will not do a 'jmp @#000000' but execute the opcode after the 'clr pc'. Walter

15 years, 9 months

FS. HP900/300 systems (Netherlands)

by roosmcd＠dds.nl

Hello, Since I need to make some more space here, the following systems are for sale. Location is The Netherlands, I can ship internationally (probably expensive), delivery in the southern part of the UK in early August might also be possble. HP9000/300 double-height enclosure (IIRC this was a 317, I'll have to check). HP-HIl audio extension 46081A HP-HIL Mouse + keyboard HP 7958 hpib disk IEM HP-IB mass storage unit with 2 3.5" floppy drives HP-IB cables + documentation HP9000/310 with keyboard and mouse and also some other stuff for sale: Philips PC200 (rebadged grid XT laptop), power supply is broken but it will also work on DC IBM 43p/140: 332MHz processor, 256MB ram and 9GB disk with regards, Michiel

15 years, 9 months

Olivier de Smet makes a very nice HP85 in fpga

by hp-fix＠xs4all.nl

http://sites.google.com/site/olivier2smet2/hpseries80/fpga-hp85b Forwarding from HP80- series yahoo group : Hi, I just wanted to inform all of you that I started a new HP8x project : Recreate HP80 series computer in modern hardware :) Some news at the following url <http://sites.google.com/site/olivier2smet2/hpseries80/fpga-hp85b> http://sites.google.com/site/olivier2smet2/hpseries80/fpga-hp85b P.S. the HP9121 emulation on SD card is near completion Olivier

15 years, 9 months

yet another pdp-11 in fgpa

by w.f.j.mueller＠gsi.de

Johnny Billquist <bqt at softjar.se> wrote: > Good thinking. > But I'm surprised by some numbers here. The J11 at 20 MHz is > only slightly faster than an 11/70. In fact, if you can throw > the 11/70 into running all from cache, it might even be slightly > faster than an 11/9x. > Or so I seem to remember from looking at the numbers back when > I last was digging into this. > > Maybe I'm mixing some numbers up here... What I do remember for > sure is that the 11/9x machines run at 20 MHz, and that they are > not more than maybe 1.2 times the speed of an 11/70 in general. oops, you are right, I was mixing numbers here and forgot about a factor of four. Here the revised arguments: See http://www.village.org/pdp11/faq.pages/prfmnc.html , there is a table comparing 11/70 with various J11 systems: 11/23 11/53 11/73 11/83 11/93 ----- ----- ----- ----- ----- CPU F-11 J-11 J-11 J-11 J-11 Microcycle(ns) 300 267 267 222 222 Clock (MHz) ? 15 15 18 18 Performance 0.2 0.5 0.7 1.2 1.4 (11/70 = 1) Cache no no yes yes no Floating-Pt opt no no yes yes Coprocessor My mistake was to forget that the J11 needs 4 clock cycles per microcycle (MC), that's why 18 MHz clock leads to 222 ns MC period. In the end the J11 (222ns MC) is faster than the 11/70 (150 ns MC) because it has a better micro architecture (three stage pipeline vs. instruction prefetch only). The J11 is roughly a factor two better compared to 11/70 in terms of MC efficiency. The w11a on the other side does one microcycle per clock cycle. So one can expect that is roughly a factor 5.5 faster than a 18 MHz J11 (MC rate is 11 times higher (50/4.5), but J11 has a factor two better MC efficiency). Let's look at the Dhrystone benchmarks again: w11a 11500 lps 11/53 830 lps So the w11a is measured to be ~14 faster than a 11/53. The 11/53 has half the performance of a 11/70, so one expects that the w11a is about a factor 7 faster than a 11/70. Because w11a and 11/70 have a similar micro architecture that should match the MC rate, and indeed it does (50/6.7). So the numbers are consistent, finally. Thanks for pointing that out. Walter

15 years, 9 months

yet another pdp-11 in fgpa

by w.f.j.mueller＠gsi.de

Johnny Billquist <bqt at softjar.se> wrote > You do know that the J11 is already designed for mP usage, except that > DECs testing of that was even more secret than the 11/74? Sure, the mP instructions WRTLCK and the TSTSET of the J11 are documented, and allow cleaner way to implement spin locks than the 'asrb hack' of the 11/74. In a future version of the w11a I'll probably also implement the instructions supported by 11/34 and J11 and make the 'processor profile' selectable at start time, much like in the simh simulator. > But FPP is among the most important things in there as well, I'd say. > Lots of software who won't be happy without it. That's true from a performance point of view. However - you can run RSX and Fortran without FPP (did this 30 years ago when the FPP broke on the 11/45 I was working with...). - you can run 2.11BSD without FPP (I'm doing that each time I boot 2.11BSD). So a FPP is very good to have, but not my highest priority. Also, it's quite a project to design, implement and verify it, with the verification, as usual, being the most time consuming part. > By the way. You don't have to worry about cache coherency. The > PDP-11/74 do not do that. Cache coherency is managed by software > on the PDP-11 (well, in RSX, since that's the only system that > supports the hardware). In short, the real hardware do not implement > any sort of cache coherency in hardware. I know, but I'll go for a cache with full cache coherency. That will make it a lot easier to try a MP hack for 2.11BSD. And RSX, if I ever get to it, will not mind. Walter

15 years, 9 months

yet another pdp-11 in fgpa

by w.f.j.mueller＠gsi.de

Johnny Billquist <bqt at softjar.se> wrote: > I wasn't aware that any prototypes ever were produced and came as > far as being functional. I thought it was just paper work that > had bee done. The 11/74 wasn't marketed, as pointed out in this thread, but a few systems were build by DEC. A picture of such 11/74 system was made available by Tim Shoppa, see http://www.trailing-edge.com/~shoppa/1174Xopen.jpg You'll nicely see the four CPUs. arcarlini at iee.org wrote: > I've read somewhere that it [PDP-11/74] was full of flat ribbon > cables and would have been a beast to maintain. Well, you see on the picture that there was quite a bit of flat ribbon cables :). The 'PDP 11/70 Multiprocessor Technical Manual (Preliminary Version)' is on bitsavers, see http://www.bitsavers.org/pdf/dec/pdp11/1174/EK-70MP-TM_PRE_1170mp_Prelim_Te… and gives you a feeling of the modules and interconnects. Walter

15 years, 9 months

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