I'm trying to find docs for monolithic systems 8009 board.
multibus I, z80, RAM ROM 2 serial, FDC.
I see references to the board online but no actual docs.
I'm looking for information (schematic) for the on board interrupt logic
and bus interface.
I've figured out enough to get CP/M 2.2 running on it but things like
interrupts,bus time out and arbitration are implemented in PALs and defy
my attempts at reverse engineering.
Even docs from another model (800X) may prove useful since similar
logic may be used.
thanks
joe lang
On Mon, Aug 10, 2015 at 1:00 PM, <cctech-request at classiccmp.org> wrote:
> From: Brent Hilpert <hilpert at cs.ubc.ca>
>
> There was also AlgolW, supported on MTS.
>
> As MTS was being mentioned earlier I was going to ask if anyone knew
> whether the AlgolW compiler was included in the available distribution.
>
?The sources are available - they were googlable - send me a note off list
and I can put together a tar image of what I have. FYI: It was written
PL/360. I did some hacking on it under TSS years ago.? IIRC Wirth did
AlgolW on the 360 at Stanford which was running one of the OS/360 flavors.
CMU ported to TSS and Michigan to MTS.
also check out:
The Programming Languages Genealogy Project
http://everything2.com/title/the+Programming+Languages+Genealogy+Project
?Clem?
> From: Paul Koning
> Every machine needs a fast memory system. CISC machines just as much,
> after all the number of memory references per operation of a given kind
> doesn't depend on the sort of CPU architecture you use.
You're forgetting the memory bandwidth for the instruction fetching. RISC
machines execute a stream of simple, low-level instructions, whereas CISC
machines tend to do fewer, (semantically) higher-level operations - and in
the process, use less memory bandwidth for instructions.
To be tedious (sorry), for example, instead of of the RISC instruction
sequence 'move register Ra to Rt1; add constant X to Rt1; move mem loc (Rt1)
to Rt2; add Rn to Rt2; move Rt2 to mem loc (Rt1)', a CISC would just do 'add
Rn to mem loc X[Ra]'. Same number of _data_ reads/writes, but a very different
count of instruction fetches.
The CISC tradeoff (fewer, slower, instructions) made sense 'back in the day',
and not just for memory bandwidth - it made for more compact code, back when
memory was in very short supply (by today's standards).
Now, of course, a number of technological changes - primarily multi-level
caches - have changed the 'sweet spot' for optimal instruction complexity,
while keeping the memory bandwidth needed for instruction fetches down.
Noel
One could always implement a KDF9 emulator and then port Randall and
Russell code (from the book).
And r.e. ALGOL68, Peter Hibbard had some sort of ALGOL68 system working on
the PDP11s at CMU I believe.
Posting this for another NetBSD developer. Please contact him directly if interested; I don?t have any additional information.
paul
> Begin forwarded message:
>
> From: David Holland <dholland-developers at netbsd.org>
> Subject: sparc20 available in boston
> Date: August 11, 2015 at 2:05:41 PM EDT
>
> I have a sparc20 sitting in my office that I need to get rid of for
> space reasons. Anyone in Boston want it? I do not have time to deal
> with shipping it, but you're welcome to try to persuade someone else
> around here to do that :-)
>
> It has a keyboard and mouse, and I think a framebuffer, but no
> monitor. There are I think two or three cpu modules, though I vaguely
> recall there being an issue with one of them. Dunno how much RAM it
> has.
>
> Deadline is Friday, although if someone speaks up by then I might be
> able to hold it until the end of the month. Otherwise it gets thrown
> out...
>
> --
> David A. Holland
> dholland at netbsd.org
> From: Johnny Billquist
> The 11/34 that I played with did not have a product from Enable. ...
> The product "my" 11/34 have came from Systime
Thanks for chasing that down. Yes, that would explain the non-meshing
memories! :-)
> In addition, a few wires needs to be changed on the backplane, there is
> a cable from a CPU card to the Systime card, and a few modifications
> required on the 11/34 CPU itself.
This all makes sense - if one can reach into the CPU, it's definitely
plausible to have an upgrade which expands the size of the PARs (unlike the
ENABLE board from Able).
Noel
> From: Chuck Guzis
> Why all this DEC stuff about Algol?
I probably started it; I just mentioned the PDP-11 one because a lot of
people already have either 11's, or an emulator up and running.
Noel
> From: Chuck Guzis
> Could it be that the presence of ECC registered SDRAM requires that
> every memory location get written before boot-up can proceed? There's
> 2GB of the stuff, so that could be the difference.
I was going to suggest that, actually. Turning on ECC in the memory in a
somewhat older HP minitower machine caused a long delay in booting while it
cleared all the memory.
Noel
Thanks Jay!
Marc
----------------------------
From: Jay Jaeger <cube1 at charter.net>
The link below is to a Google Drive folder with three files that I will
leave up for a while:
awstape.c - Read a SCSI tape, output in AWS format (Linux)
awstoraw.c - Read an AWS file, output a raw byte stream
awstosimh.c - Read an AWS file, output a SimH
https://drive.google.com/folderview?id=0B2v4WRwISEQRfi1TWnlKU1hqUXphWVhpZ1FK
OGFoVjRPVnppX1F2aUMwTUw0QkxSNEsyMjg&usp=sharing
They are anything but elegant, but have gotten the job done for me.
JRU
--------------------------