>That's what I wanted. I don't have any 8" drives, so adding support for them
>is pointless. Ideally, I want a board that has a 6502-type interface on one
>side and a 34-pin IDC connector on the other, with support for most common FM
>and MFM 3.5" and 5.25" formats.
I did a fairly simple 765 based controller in my D6809 which does 5.25" DD
disks (should work ok with 3.5" DD) - it has a 6809 bus on one side and a
34-pin connector on the other. It was designed mid-80's, and uses a 765, 9216,
LS175, LS153, LS161, LS174, LS139 as well as floppy bus drivers/receivers, and
a couple of LS04 gates and one LS00 gate borrowed from elsewhere in the system
(The whole computer was one big wire-wrap board - you can see it on my site).
I don't pretend it's the most efficient design, but it was (relatively) low
parts count and worked well for me - you are welcome to it if you want it.
>I managed to get DMA-mode transfers working, but never managed to get polled-
>mode or interrupt-mode transfers working. Guess I'll have to learn fast when
>I start writing code to drive the FDC...
I did polled drivers on the 09 and it worked well. One thing I did find was
that I had to connect a select to the TC pin so that I could pulse it to end
a transfer - I did not find a way to cleanly end a transfer in polled mode
without TC. I can give you the 6809 driver code as well if you want it.
Regards,
Dave
--
dave04a (at) Dave Dunfield
dunfield (dot) Firmware development services & tools: www.dunfield.com
com Collector of vintage computing equipment:
http://www.parse.com/~ddunfield/museum/index.html
>
>Subject: Re: Floppy controller questions
> From: Philip Pemberton <philpem at dsl.pipex.com>
> Date: Tue, 23 Aug 2005 22:47:06 +0100
> To: cctalk at classiccmp.org
>
>In message <0ILO00FI3MXS1LM0 at vms048.mailsrvcs.net>
> Allison <ajp166 at bellatlantic.net> wrote:
>
>> Write clock sets the write data rate and should corrospond to the
>> rate needed for media. Writeclock is 2x data rate.
>
>Does this apply to both FM and MFM? The datasheet suggests a 500kHz WrClk for
>FM and 1MHz for MFM mode, which would give a 250kHz FM data rate and a 500kHz
>MFM data rate. Is that right?
They are right. MFM requres twice the clock of FM as it's twice the speed.
Obvious to me. However the statement is valid as the APPLIED clock is 2X
the DATA rate for any mode.
One of the confusing issues the fact that when going to MFM (AKA Double Density)
you will always run the clock twice that of FM but the ratios of Wclock to data
rate is always 2. The MFM pin can be used to select Wclock or Wclock/2 for
MFM/FM operation on write and for read it can select clock or other timing
dependent control for the read_data and read_data_window recovery.
Oh and BTW: those specified data rates would be for 8" drives. For 5.25
they are half that.
>And RdWindow from the datasep should cover the read frequency variations,
>assuming the datasep can handle the variation in mode and frequency.
Assuming you condition the data seperator for the correct mode with
MFM output from the FDC.
>> the logic does things like Data Clock recovery, Write precompensation timing
>
>I've heard the term "write precompensation" thrown about a bit - what's the
>purpose of it?
Simply put when you write flux transistions close together they tend to
push apart or attract (depnding on adjacent flux transistions on media
causing time distortion. Write precom is a predistortion based on the
bit pattern so the recovery windows will be better. More important to
MFM than FM. Some drives tend to distort more than other based on head
design and write currents used.
>> Using a 765 for _all_ data rates and both 3.5"/5.25"/8" floppy interfaces
>> implemented with LSttl fills a S100 board completly.
>
>That's why SPLDs (GALs) and CPLDs were invented I guess. Squish the address
>decoder, interface logic, and the data separator into a few LSTTLs and GALs,
>or just throw everything into a single CPLD :)
Yep, helped design and test a mask programmed gate array that reduced the
minimal base PC from about 15 chips to less than 7 while keeping a good
data sep and write precomp logic.
>> Most designs implemented a subset for 8" or 5.25"/3.5" only
>> (jumper selected) with much lower parts cost.
>
>That's what I wanted. I don't have any 8" drives, so adding support for them
>is pointless. Ideally, I want a board that has a 6502-type interface on one
>side and a 34-pin IDC connector on the other, with support for most common FM
>and MFM 3.5" and 5.25" formats.
Well the interface for 3.5 and 5.25 are nearly identical and that made most
of that simple. the only real differnce is you will likely run twice the clock
rates for 3.5" drive than 5.25".
>> Yes, it was done on the 1.2MB AT-class machines. Reminder: every PC with
>> rare exceptions used a 765 or a derivitive based on the 765 core.
>
>So I've noticed. I managed to get DMA-mode transfers working, but never
>managed to get polled-mode or interrupt-mode transfers working. Guess I'll
>have to learn fast when I start writing code to drive the FDC...
Polled mode is tricky as the loop must wait for data to be ready then
transfer it. That loop can be as fast as 13us worst case for DD 8"
or 1.44mb 3.5". If your slow you get data overrun errors.
>> For MFM is when the transiston occurs rather than how many. Generally the
>> Floppy generates what is by standard expected and the FDC external logic
>> will regenerate data pulses and data window (data window is a read clock).
>
>Right. So with FM the datasep syncs to the high-frequency signal in Gap1,
>then every time there's a 0 you'll pick up a 0/1/0/1 sequence for each read
>window, and when there's a 1 you'll pick up a 1/1/1/1 sequence?
>
>And with MFM, a 0 after a 0 would be 1/0, a 0 after a 1 would be 0/0 and a 1
>would be 0/1?
Not always. The rate of transistions and symbols (zero or one) may not be
one to one for number transistions. Never quite got MFM in my head as
clear as FM.
>
>0/1 taken to mean "first data window was empty, second had a pulse in it".
More like a 0 was a longer window than a one. where the FM the window
always has one transistion and if it's a one then there will be a
transistion near the middle of the window.
The trick with floppies is the drive has a narrow bandwidth and the typical
data rate must be in the range of F and 2F where F is some number of flux
transistion per unit time (and also realated to per inch at rotation speed).
MFM does some long string things to get the number of transistions to stay
within F and 2F bit does not have the clear 1:1 symbol corolation of FM.
Of course in real life not much of this is needed to assemble a working
FDC/Floppy interface.
Allison
>From: "Allison" <ajp166 at bellatlantic.net>
---snip---
>
>>> For MFM is when the transiston occurs rather than how many. Generally the
>>> Floppy generates what is by standard expected and the FDC external logic
>>> will regenerate data pulses and data window (data window is a read clock).
>>
>>Right. So with FM the datasep syncs to the high-frequency signal in Gap1,
>>then every time there's a 0 you'll pick up a 0/1/0/1 sequence for each read
>>window, and when there's a 1 you'll pick up a 1/1/1/1 sequence?
>>
>>And with MFM, a 0 after a 0 would be 1/0, a 0 after a 1 would be 0/0 and a 1
>>would be 0/1?
>
>Not always. The rate of transistions and symbols (zero or one) may not be
>one to one for number transistions. Never quite got MFM in my head as
>clear as FM.
>
>>
>>0/1 taken to mean "first data window was empty, second had a pulse in it".
>
>More like a 0 was a longer window than a one. where the FM the window
>always has one transistion and if it's a one then there will be a
>transistion near the middle of the window.
>
>The trick with floppies is the drive has a narrow bandwidth and the typical
>data rate must be in the range of F and 2F where F is some number of flux
>transistion per unit time (and also realated to per inch at rotation speed).
>MFM does some long string things to get the number of transistions to stay
>within F and 2F bit does not have the clear 1:1 symbol corolation of FM.
>
>Of course in real life not much of this is needed to assemble a working
>FDC/Floppy interface.
>
>
>Allison
>
>
Hi
My understanding was that both FM and MFM have the same
maximum average flux change rate. As I recall, FM was a
two cells for each data bit. clock in one and data in the other.
MFM was where in the cell the bit was found. If it was
early, it was a clock and late, it was the data bit. There
were some rules about placing two transitions right next
to each other so that a data "1" couldn't be followed by a clock.
The frequency of the input clock to the FDC needs to be
2X for the MFM because it has finer timing edges, otherwise the
average rate of pulses to the drive is the same.
For soft sectored, they had some special marks that violated
the rules for where a clock pulse should exist. The controller
would watch for the missing clock and then recognize the data
to determine what type of marker it was. This located things
like header fields and data fields.
I hope I got that right.
Dwight
>
>Subject: Floppy controller questions
> From: Philip Pemberton <philpem at dsl.pipex.com>
> Date: Tue, 23 Aug 2005 14:19:52 +0100
> To: cctalk at classiccmp.org
>
>Hi folks,
> I've been reading through the uPD765, R6765 and 8272 FDC datasheets. All of
>them seem to cover the basics pretty well, but I've got a few quick questions
>for anyone who's used a 765-type FDC (or any other FDC that behaves in a
>similar way), or who knows a bit about floppy drive technology:
>
> 1) How do you vary the read/write data rate? Some 3.5" formats use MFM at
>250kbits/sec, others use MFM at 500kbits/sec. What relation does the WRITECLK
>input have to the data rate of the MFM-coded signal at the WRITE DATA output?
>What about the 8MHz master clock?
BY prescaling the clock. Master clock drive the internal cpu and
after prescaling the various timers (step rate, Head load time,
head unload time) Possible useful rates for Clock is 8 and 4mhz.
Use 8MHZ for fastest step rates, 4mhz for those drives (like sa400)
that need really slow step rates. Also the rate that the master
status register is updated is affected due to internal microprocessors
speed.
Write clock sets the write data rate and should corrospond to the
rate needed for media. Writeclock is 2x data rate. The master clock
is not synchronous to the write clock though it's easiest to derive
both from the same master source.
NOTE: like the 179x/177X basic controllers the 765 requires external logic
to scale clock rates, write clock rates demux the various drive interface
lines and generate the correct levels for driving the disk drive. Additonally
the logic does things like Data Clock recovery, Write precompensation timing
as those functions required logic faster than was doable in NMOS in 1981.
The second generation chips such as 9266 and later WD37C65 integrated
most of that logic into the chip in the AT-PC style (subset of full capability).
Using a 765 for _all_ data rates and both 3.5"/5.25"/8" floppy interfaces
implemented with LSttl fills a S100 board completly. Compupro, IMS and others
are examples. Most designs implemented a subset for 8" or 5.25"/3.5" only
(jumper selected) with much lower parts cost. A design for 5.25/3.5 floppy
(no 5.25 1.2mb) only can be simplified further for greater parts savings.
Single sided and double sided are trivial and add nothing to the design.
The bulk of the logic is in five groups, bus interface, general clock
generation, Write logic (clocks and precomp), read logic (aka seperator)
and floppy interface.
> 1a) Can the uPD765 be made to read and write both DSDD and DSHD floppies?
>If so, how? I know the WD 177x controllers could do it if the 8MHz master
>clock was increased to 16MHz (an old trick used on Acorn A3000s). Does the
>same trick work with the 765?
Yes, it was done on the 1.2MB AT-class machines. Reminder: every PC with
rare exceptions used a 765 or a derivitive based on the 765 core.
Write clock needs to be scaled to the correct value. OR you can take
advantage of the HS lone on some drives so that the FDC can be clocked
at 500khz data rate rather than the odd (non sub-multimple of 16mhz)
600/300kHz. Some designs used a 24mhz master clock to derive 8mhz,
4mhz, 1mhz, 600khz, 500khz, 300khz, 250khz, 125khz as needed for the
correct data rates. Other timing derived from the master clock is
the timing for the precomp shift register.
> 2) How does the FDC decode the data it's been given, based on the data
>window and the data read from the disc? In FM mode I guess you'd count the
>cycles within the data window - 2 would be a 0, 4 would be a 1. But what
>would you do for MFM?
For MFM is when the transiston occurs rather than how many. Generally the
Floppy generates what is by standard expected and the FDC external logic
will regenerate data pulses and data window (data window is a read clock).
>
> 3) What happens when the drive's head picks up a flux transition? Does the
>the drive generate a single pulse every time the head hits a transition, or
>does the drive's RD DATA output change state?
Pulse every transistion. By standard, the singal from the Floppy is a negative
going pulse with pull up to 5V.
> 4) When writing data, I'd guess that setting WR DATA high would polarise
>the magnetic coating one way, while setting it low would polarise it the
>opposite direction. Is this how it works, or does the WR DATA line get pulsed
>to make the drive put down a flux transition?
Pulsed to cause a transistion.
FDCs are not transistion polarity selective. The critical parameter is
that there was a transistion and when it occurs. The stated FRPI (flux
reversals per inch) determine the media density and MFM uses fewer reversals
per bit than FM so the density can be higher. In the density scale the
8" SD is the lowest and the 1.44mb 3.5" highest.
There is a lot here.
Allison
>
>Subject: Re: Floppy controller questions
> From: ard at p850ug1.demon.co.uk (Tony Duell)
> Date: Tue, 23 Aug 2005 20:15:48 +0100 (BST)
> To: cctalk at classiccmp.org
>
>> > 1) How do you vary the read/write data rate? Some 3.5" formats use MFM at
>> >250kbits/sec, others use MFM at 500kbits/sec. What relation does the WRITECLK
>> >input have to the data rate of the MFM-coded signal at the WRITE DATA output?
>> >What about the 8MHz master clock?
>>
>> BY prescaling the clock. Master clock drive the internal cpu and
>> after prescaling the various timers (step rate, Head load time,
>> head unload time) Possible useful rates for Clock is 8 and 4mhz.
>> Use 8MHZ for fastest step rates, 4mhz for those drives (like sa400)
>> that need really slow step rates. Also the rate that the master
>> status register is updated is affected due to internal microprocessors
>> speed.
>>
>> Write clock sets the write data rate and should corrospond to the
>> rate needed for media. Writeclock is 2x data rate. The master clock
>> is not synchronous to the write clock though it's easiest to derive
>> both from the same master source.
>
>To avoid confusion. I think it would be clearer to say that Write clock
>_need not be synchornised_ to the master clock. As you go on to say,
>there is no problem if Write clock is derrived by dividing down the
>master clock signal (asusming that will give the data rate you want), in
>fact just about every floppy controller board does it that way.
\
Err, I said that, did I not?
Two people seperated by a common language.
Allison
> I am suprised there are no floppy drive schematics on bitsavers...
there are probably a dozen in the service manuals
qume, shugart, teac, siemens, for example.
http://www.bitsavers.org/pdf/siemens/FDD100-8_V2.pdf
has a pretty good circuit description of a single sided
drive.
Anyone need a PC jr. with the (nonchiclet) keyboard and monitor? They are
officially in the way. Cheap.
Also, anyone need TRS-80 modems - specifically a Modem 1 and Modem 1B, and
new in box Acoustic Coupler? Cheap, also.
William "zip is 10512" Donzelli
aw288 at osfn.org
Hi folks,
I've been reading through the uPD765, R6765 and 8272 FDC datasheets. All of
them seem to cover the basics pretty well, but I've got a few quick questions
for anyone who's used a 765-type FDC (or any other FDC that behaves in a
similar way), or who knows a bit about floppy drive technology:
1) How do you vary the read/write data rate? Some 3.5" formats use MFM at
250kbits/sec, others use MFM at 500kbits/sec. What relation does the WRITECLK
input have to the data rate of the MFM-coded signal at the WRITE DATA output?
What about the 8MHz master clock?
1a) Can the uPD765 be made to read and write both DSDD and DSHD floppies?
If so, how? I know the WD 177x controllers could do it if the 8MHz master
clock was increased to 16MHz (an old trick used on Acorn A3000s). Does the
same trick work with the 765?
2) How does the FDC decode the data it's been given, based on the data
window and the data read from the disc? In FM mode I guess you'd count the
cycles within the data window - 2 would be a 0, 4 would be a 1. But what
would you do for MFM?
3) What happens when the drive's head picks up a flux transition? Does the
the drive generate a single pulse every time the head hits a transition, or
does the drive's RD DATA output change state?
4) When writing data, I'd guess that setting WR DATA high would polarise
the magnetic coating one way, while setting it low would polarise it the
opposite direction. Is this how it works, or does the WR DATA line get pulsed
to make the drive put down a flux transition?
Thanks.
--
Phil. | Acorn RiscPC600 SA220 64MB+6GB 100baseT
philpem at philpem.me.uk | Athlon64 3200+ A8VDeluxe R2 512MB+100GB
http://www.philpem.me.uk/ | Panasonic CF-25 Mk.2 Toughbook
... How's this for diplomacy? Shoot them all! --Kirk
I found what I believe to be an NCR Decision Mate V computer. 1 5.25
floppy drive and 1 hard drive.
no docs, no keyboard, no disks.
Does anyone have info on this computer and any idea how to get a
keyboard for it?
thanks!
-Bob
--
bbrown at harpercollege.edu #### #### Bob Brown - KB9LFR
Harper Community College ## ## ## Systems Administrator
Palatine IL USA #### #### Saved by grace
