On Apr 22, 23:01, Tony Duell wrote:
> > I thought of that too. Then you might be able to do it with an AOI
package,
>
> Oh, AOIs are fun, but not general enough for this...
You tend to need more than one small package to anything very useful
> > but I'd use a 156, which is a demultiplexer/decoder but with open-collector
> > outputs, which I'd wire-AND.
>
> Good guess. What you need is a fixed AND matrix to get all the possible
> product terms and then a programmable OR matrix to combine the right ones
> to form the desired output.
>
> That's _exactly_ what a PROM is, of course.
>
> It's also what a multiplexer is.
A neat solution. Of course, anything you can do with minterms can also be done
with maxterms.
> What worries me is that the above seems not the taught any more. And
> people don't seem to have grown up fiddling with TTL chips (or
> equivalent).
Here, 1st Year CompScis do a series of practical problem exercises with TTL,
one of which ends up building a multiplexer from basic gates. The next (or
maybe next but one) involves something that's complex to do with normal minterm
techniques, and often involves using a multiplexer as a building block.
--
Pete Peter Turnbull
Dept. of Computer Science
University of York
On Apr 22, 19:12, Allison J Parent wrote:
> LSI-11/03 cpu and box. The backplane was wired for only 16bit addesses.
> Also that particular CPU put some of the microcode signals on what would
> have ben the A16-21 lines.
Nitpick: Actually, it's wired for 18-bit (it has to be, for parity), and the
extra microcode signals are only on the A18-21 lines.
You can have fun with General Robotics backplanes/PSUs. Some of these put 24V
AC on the lines normaly used for A20 and A21.
--
Pete Peter Turnbull
Dept. of Computer Science
University of York
But, since Alphas must share SOMETHING in common with the PDP-11,
wouldn't it be possible to write a normal program for the Alpha,
running under NT or Linux, that would give PDP emulation at P-II-like
performance? Of course, I'm assuming that some of the PDP instructions
can go unchanged directly into the Alpha. Also, I would guess that a
G3 with an emulator could outperform the slower pentiums. But, then
again, why not emulate a Whirlwind or a Mark I for the same? It would
be much easier. I don't really see how an emulated PDP-11 outper-
forming a pentium would mean anything at all.
Now, making a VAX that would do that is a bit more interesting, though
probably already done. VAX is much more useful these days than PDP-11.
More on this subject: I have long thought that some computers that
are now mostly PD, like the C-64, should be rebuilt in kit form and
sold to kids for $20 each. Now THAT would be nice. Oh, and make them
make their own kernel, and hold a contest for the best one. The
winner gets an emulated PDP-11.
I really must stop eating sugar as well.
>incremented value) and three for JSR I Z 10 (fetch 10, write
incremented
>value, stash return address at location pointed to by incremented
value),
>so I could be wrong) each of which depend on the previous one. You're
not
>going to get hot performance out of that unless you decide that the
main
>memory can be built using a 5-port register file on the chip.
>
>I've occasionally wondered about doing a tight hand-coded PDP-11
emulator that
>fits in the primary cache of an Alpha. If possible, you'd be using the
Alpha
>essentially as a programmable microengine and programming it to be
PDP-11.
>The reason to fit it in the primary cache is because of how the Alpha
boots;
>at reset, it loads its primary cache from an external serial ROM and
begins
>executing it. If you could fit the emulator in the primary cache, you
could
>think of the Alpha+SROM as a PDP-11 microprocessor.
>
>Roger Ivie
>ivie(a)cc.usu.edu
>
______________________________________________________
Get Your Private, Free Email at http://www.hotmail.com
What would happen if we made a PC-sized PDP-11 processor using the Alpha
technology? (On a single chip, clock it at ~300-400 MHz)
As the PDP-11 instruction set is MUCH better than 80x86, would it outrun
a PC? Could this be a Pentium Killer?
-------
<>As the PDP-11 instruction set is MUCH better than 80x86, would it
<outrun
<>a PC? Could this be a Pentium Killer?
as it was in 1982-3 the PCversion of the PDP-11 aka PRO350 could eat
the XT and turbo XT for a snack. When the AT came around DEC popped
out the pro380 with the J-11 cpu...gulp, burp! ATs are tasty.
Competing against the mostly 16bit 8088/6 and the 286 the PDP11 was out
front. To match a 16bit cpu against a 32bitter... you must be inhaling!
Allison
After your done laughing remember this...
At the time the VAX was new in the market the PDP-11 group took most of
their standard 11/70 peices and cooked up the 11/74 which was a 4cpu SMP
11/70 and could eat vaxen(11/780) for snacks. That was it's demise...
there were only four working 11/74s built before that was crushed.
<Hmm, refresh my memory, now what were the PDP-11 instructions to
<directly address 4GB of memory? I can't seem to recall any 32 bit
<address registers.
Look in the VAX archectecture book.
<Darn. I've really lost it...how did the virtual memory hardware work in
<a PDP-11?
Nicely (again the vax is a mostly stretched 11).
<Seriously, if you mean the sorta RISC like instruction set in the 11 is
RISC?????? PDP-11 is the most CISC machine in the 16bit realm. What
other 16bitter is a two address orthoginal machine?
<better than the x86 set, then DEC probably would have come up with
<something like that. Course, with extra silicon, they could have gone
<to 64 bits, and put more cache onboard, then clock it really fast. Then
<come up with some catchy marketing name, like Gamma, or Beta, or ....
They did called it VAX and when it came time to outvax VAX then comes
alpha.
Allison
<Um... Am I way out here? Doesn't the 23 support 22 bit addressing? And
The basic M8186 early revs are 18bit but most work as 22bit, the later
revs were 22bit. That's assuming the backplane is wired for 22bit as
well.
<I never before heard of a 16 bit Qbus! ISTRT the F11 processor is
LSI-11/03 cpu and box. The backplane was wired for only 16bit addesses.
Also that particular CPU put some of the microcode signals on what would
have ben the A16-21 lines.
<settable between 18 and 22 bit (128KW, 256KB and 2MW, 4MB respectively).
<The 18 bit setting is used in the 23 on 18 bit Qbuses and in the 24 on
<unibuses. The 22 bit setting is used on 22 bit Qbuses, but you need
<extra hardware to use it in the 24 (i.e. on unibus).
Your thinking of latter machines with specific backplanes.
Allison
> What would happen if we made a PC-sized PDP-11 processor using the Alpha
> technology? (On a single chip, clock it at ~300-400 MHz)
> As the PDP-11 instruction set is MUCH better than 80x86, would it outrun
> a PC? Could this be a Pentium Killer?
I doubt it could be a Pentium killer, but I could be wrong. The RISC
machines get performance by making it difficult to go to memory; on the
PDP-11, it's much to easy to go to memory.
Take, for example, the PDP-8. The worst-case instruction on the PDP-8
could require as many as five memory accesses (hmm; I forget which one
took five. I only count four for ISZ I Z 10 (fetch 10, write incremented
value, fetch from incremented value, write incremented value pointed to by
incremented value) and three for JSR I Z 10 (fetch 10, write incremented
value, stash return address at location pointed to by incremented value),
so I could be wrong) each of which depend on the previous one. You're not
going to get hot performance out of that unless you decide that the main
memory can be built using a 5-port register file on the chip.
I've occasionally wondered about doing a tight hand-coded PDP-11 emulator that
fits in the primary cache of an Alpha. If possible, you'd be using the Alpha
essentially as a programmable microengine and programming it to be PDP-11.
The reason to fit it in the primary cache is because of how the Alpha boots;
at reset, it loads its primary cache from an external serial ROM and begins
executing it. If you could fit the emulator in the primary cache, you could
think of the Alpha+SROM as a PDP-11 microprocessor.
Roger Ivie
ivie(a)cc.usu.edu
Seth and Pete were discussing the PDP11-23...
>> 2) Same as above, but for the M8044-DB boards. I could put one
>> of these in with the M8047's to get a full 64Kword of RAM, yes?
>> Does anyone know what the DIP-switch settings for these boards
>> are?
>
> Yes, but I'm not sure why you say "full" and 64Kword" together :-)
> 32KW (64KB) is the limit for 16-bit addressing, or 128KW (256KB) for 18-bit
> addressing. Ignoring the I/O page, that is.
Um... Am I way out here? Doesn't the 23 support 22 bit addressing? And
I never before heard of a 16 bit Qbus! ISTRT the F11 processor is
settable between 18 and 22 bit (128KW, 256KB and 2MW, 4MB respectively).
The 18 bit setting is used in the 23 on 18 bit Qbuses and in the 24 on
unibuses. The 22 bit setting is used on 22 bit Qbuses, but you need
extra hardware to use it in the 24 (i.e. on unibus).
Just my half groat's worth.
Philip.
On Apr 22, 1:57, Tony Duell wrote:
> Jack Peacock wrote:
> > 'No, I can do it with a normal 16 pin TTL chip that doesn't have to go
> > in a programmer first'. So, what was the chip ?
> >
> > 74LS138, 1 of 8 decoder, the three inputs go to A, B, C, all 8
> > possibilities decoded on the outputs.
>
> Alas not.. I didn't want the 8 separate combinations of the 3 input
> variables - I wanted a single output that was a complex function of them
> - something like A.C + A.B/ + A/.C/.B or something...
I thought of that too. Then you might be able to do it with an AOI package,
but I'd use a 156, which is a demultiplexer/decoder but with open-collector
outputs, which I'd wire-AND.
--
Pete Peter Turnbull
Dept. of Computer Science
University of York
