24 Jan
2006
24 Jan
'06
5:01 p.m.
On 1/24/2006 at 4:24 PM Brent Hilpert wrote:
Chuck Guzis wrote:
What would the address selection logic look like? For 32K, it would be
7x8. For writing, I suppose you could use some steering diodes at each
relay and supply somewhat less than the pull-in current needed on the x and
y access, so that the addressed relay wouldn't pull in unless both x and y
signals were present.
I suppose readout could be accomplished with another set of contacts on the
select relays.
Doing a 32Kx8 would doubtless require some significant timing delays to
allow for mechanical settling of the relay contacts.
Mechanical systems can be very interesting.
Old pipe organs (before the advent of electronics and electricity) used a
mechanical memory to record the states of adjustable combinations. Usually
accomplished by flipping pawls one way or the other.
IIRC, the big Univac drum used on the 1107/1108 systems (FASTRAND II?) used
a mechanical system to position the heads. Essentially a system of levers
driven by solenoids(?) that decoded a binary signal into an absolute
position.
...and then there's the way a Teletype decodes incoming serial data that's
very clever.
Cheers,
Chuck
Let's think about this...
Could you really make a memory cell with 1 relay per bit using standard
relays? Latching relays, perhaps, but regular "make on coil
current/break
on no current" relays?
How about:
- use regular relays as you suggest, n+1 relays per word,
n relays are 'bit relays', the (n+1)'th relay is a 'clear relay'.
- a contact of each of the n bit relays is wired to latch the relay.
- a normally-closed contact on the clear relay of each word
supplies power to the latch contact for the n bit relays.
A write cycle for the word consists of the sequence:
1. pulse the clear relay for the word
(opens the latch circuit, bit relays are released)
2. 'gate' the data bus onto the coils of the bit relays,
the relays for bits="1" pull in and latch up.