I completely agree about the Saleae devices. Very good software, nicely made hardware. They're not cheap though, and only go up to 16 channels. You can capture 16 channels with the very cheap Cypress FX2 dev boards (the older Saleae devices were pretty much that). I'd like to find a convenient solution for more width though - I have an HP16500B but it's huge and noisy. There are one or two possibilities in the sigrok hardware list but nothing I've tried yet. On Tue, Mar 14, 2023 at 1:28 AM Jim Brain via cctalk <cctalk(a)classiccmp.org> wrote:

Be careful about throwing stones if you are living in a glass house. On Tue, 14 Mar 2023, 6:49 pm Peter Coghlan via cctalk, < cctalk(a)classiccmp.org&gt; wrote:

Alfred Arnold's AS assembler is working very good for with your mnemonics for PALM assembly. We debugged a few issues (including also that he supports the original IBM mnemonics - he had a few inconsistencies on those, but I think we got them all ironed out -- but in any case, I much prefer your mnemonics anyway). His newer AS build/updates as of this month should have all those fixes. I started preparing a library of assembly functions for basic things (like binary to decimal string conversion), and polling keyboard inputs - standard things I'd need to build up to the terminal program. Along the way, I got sidetracked into making this demo that I think is the first time anyone has showcased a special feature of the IBM 5110 character set: https://www.youtube.com/watch?v=m5ewb1BOgzE I got the DB25 pins wired up, and was going to start experimenting with those GETB, PUTB, CTRL and STAT opcodes. I don't have any actual serial IO card for the 5100 - but I figure I should be able to purely "bit bang" off the external IO in my own main-loop. It might only get 50 or 110 baud, but I'm fine with that -- anything to let me stream in some code without having to re-type it. Input would be the first goal: monitor the 8 data lines on the external pins, start writing one byte at a time to RWS (and just do something like press spacebar to toggle the writing). Then I use an MCU connected to those 8 data lines with some TBD timing (probably 330ohm resistors inline?). And I only need to support streaming in machine code (a binary produced by AS). That is, find some minimal bootloader (using GETB and CTRL?) to load a larger terminal program - then that terminal program should be able to interface with a WiModem ("RS232" device connected up with 3 pins). I'd be happy to just get the input loader working for starters, but I can't use the 5110 emulator for that and have to be hands on with the real system. That's the dream, anyway. My internal cassette deck on that system is still working, but that may not last forever (and in any case, I can't write new code from the PC onto a QIC tape in a format the 5110 understands). Note, I'm booked to go to VCF East this year, if anyone wants to talk 5100/5110 stuff. -Steve

Yes, I've used sigrok and sat on their IRC channel for quite a while. I've used the gpib analyser and extended a DMM driver to cover the hp34401A. The logic analyser client is probably the best application and is comparable with Saleae's own client. The streaming cli clients are also good, but I think the scope client is behind Zonenberg's glscopeclient. Sigrok is generally pretty good but is suffering developer shortage at present. The code quality is very good so this doesn't create a bug fixing issue but it does mean some recent feature additions haven't made it to the mainstream. If you (or anyone) has a taste for code reviewing I believe you'd be very welcome to help. I've also seen a recent patch to make it easier to use out-of-tree drivers for this very reason. I don't know much about that but it's an op[tion if you want to use the rasbperry pico as an acquisition engine. Open source and cross-platform credentials are excellent : in fact this causes a slight problem, as the Cypress FX3 which would otherwise be a good candidate as an acquisition engine can only be shipped with closed-source proprietary blobs, which stops it being used by sigrok. Any errors in the above are my own.. On Tue, Mar 14, 2023 at 2:39 PM Paul Koning via cctalk < cctalk(a)classiccmp.org&gt; wrote:

Often that's true. The issue I'm fighting right now is on a baseband data transfer which occurs at 11k per second, and some of them seem to be getting messed up. So there are long gaps in between. I only see one or two of them before memory runs out. It may be what I need to do is unplug the serial link, which is running with a continuous clock (6 MHz or so), that's probably sucking up buffer entries. The analyzer I have is a Philips PM3585 -- 96 channels (though I don't have a full set of cables and pods), 2k samples. So in theory, with some care and enough wires unplugged, I should be able to see 100 or 200 cycles of the problematic transfers. That might just be good enough. paul

A brief description of "built-in" FPGA logic analysers seems worthwhile, a valuable if non-trivial option. Most FPGA vendors provide IP to implement in vivo logic analysers organically in the FPGA fabric. Additionally, they provide a GUI to display / capture the data and to interactively configure qualifiers and triggering. The capabilities provided by AMD Xilinx, in Vivado, provide a good exemplar. https://docs.xilinx.com/r/en-US/ug936-vivado-tutorial-programming-debugging… https://www.xilinx.com/products/intellectual-property/ila.html https://www.xilinx.com/video/hardware/introduction-to-the-vivado-logic-anal… Pods such as the Digilent digital discovery, based on a Spartan-6 FPGA, mentioned in my previous post typically use a USB host interface. The Vivado ILA typically uses the (JTAG) programming link. Consequently, the commercial LA pods and ILA technology are probably best viewed as cousins, interoperation may be possible but is not a given. The standard use case for an ILA is during FPGA code (VHDL or Verilog) development, where the focus is on the internal FPGA logic; e.g. providing an execution trace for a SIMD sequencer, for debug or verification. The use case Syste suggests is to connect a UUT to an FPGA (board) with the interest now in the external signals and logic; e.g. connecting an ADC EVB to an FPGA EVB to firstly inspect the interface signals and then exploit the data stream. Equally, as Syste suggests, a suitable FPGA EVB could simply be employed as a logic analyser. The capability of the ILA will of course be bounded by the available resources and one's deviousness: - JTAG interface : in general, neither slow not fast - fast memory for acquisition and buffering : on a low end FPGA / SOC - 1 to 2 Mbits of ~4 ns access time BRAM The "cost" of this "free" technology needs to be noted: - the FPGA EVB and JTAG interface will be relatively inexpensive - the FPGA vendors ILA IP and tools typically free - the XFU (exercise for User) elements are where the cost lies -- integrating UUT and FPGA EVB : modest effort / cost ? -- mastering Vivado, the ILA IP and block diagram configuration, VHDL/Verilog, timing constraints, ... In summary, a useful capability is available but without FPGA expertise exploitation would be difficult without a canned example Martin === From: Paul Koning via cctalk [mailto:cctalk@classiccmp.org] Sent: 14 March 2023 14:40 I noticed the sigrok.org devices list mentions one that is open source hardware, that sounds a bit like what Sytse was talking about. paul ==== From: Sytse van Slooten via cctalk [mailto:cctalk@classiccmp.org] Sent: 14 March 2023 12:33 Another option that I haven't seen mentioned: use the built-in logic analyzers that the fpga tool chains come with - you'd have to wire up an fpga and sample the signals you need, but all the complexity of triggering, buffering and displaying would be done by the tool chain. -- Sytse ==== From: Martin Bishop via cctalk [mailto:cctalk@classiccmp.org] Sent: 14 March 2023 07:51 https://digilent.com/shop/digital-discovery-portable-usb-logic-analyzer-and… 32 ch at 200 MS/s and pleasantly inexpensive If I was buying, I would consider trying one

I also use the pctestinstruments. One of its strong points is that it plays well with virtualbox - I run it in a W7 guest on my centos desktop. The buffer depth is usually a bit limiting though, and triggering is also somewhat basic. Another option that I haven't seen mentioned: use the built-in logic analyzers that the fpga tool chains come with - you'd have to wire up an fpga and sample the signals you need, but all the complexity of triggering, buffering and displaying would be done by the tool chain. -- Sytse