There's a small detail that's in the document: some of the GPIO pins double as analog inputs (for the ADC). Those, unlike the other GPIO (digital only) pins, are not 5 volt tolerant. Four of the GPIO pins brought out to the edge of the Raspberry Pico board are those analog/digital combo pins, so for any 5 volt work you'd have to avoid directly connecting 5 volt devices. paul

It doesn't say that in the revision history chapter. Instead, it doesn't say at all, which makes people wonder if this is a documentation fix for something that always was there, a now documented capability because of better chip qualification, or if it really is a revision dependent feature that isn't correctly documented as such? paul

Yikes. Assuming that is accurate, Raspberry Pi screwed up very severely by claiming 5V support in the data sheet without saying it only applies to the A4 rev. Any number of people will fry their chips because of this blunder. paul

What about output pins in open-drain mode with a 5V pullup ? Can they provide a 5V CMOS-compatible output ? On Wed, Jul 30, 2025 at 9:40 PM Paul Koning via cctalk <cctalk(a)classiccmp.org> wrote:

I was thinking specifically of ws2812 addressable leds which have CMOS levels. The data stream is fairly slow (~800kHz) and can usually be generated from 3v3 with the common FET voltage shifter (which also has passive pullup). It's sometimes driven with 3v3 but is marginal. I was thinking that it might be driven bye a 2350 with a 5V pullup more reliably. On Wed, Jul 30, 2025 at 11:19 PM Martin Bishop <mjd.bishop(a)emeritus-solutions.com> wrote:

On Wed, Jul 30, 2025 at 3:25 PM Paul Koning via cctalk <cctalk(a)classiccmp.org> wrote: I seem to remember them talking about 5V tolerance as a new feature in the original RP 2350 announcement, and it was a thing in my head at least before I heard about the new revision.

Iff a device has a 5V tollerant input and the device at the other end is TTL that is essentially what you are doing - fitting a real level shifter In the case of the RP2050, subject to the mask revision being A4 ... Martin -----Original Message----- From: emanuel stiebler [mailto:emu@e-bbes.com] Sent: 30 July 2025 22:07 To: General Discussion: On-Topic and Off-Topic Posts <cctalk(a)classiccmp.org>rg>; Martin Bishop <mjd.bishop(a)emeritus-solutions.com> Cc: Paul Koning <paulkoning(a)comcast.net> Subject: Re: [cctalk] Re: RP2350 5V Input Tollerant Pins On 2025-07-30 16:15, Paul Koning via cctalk wrote: Just put real level shifter on the board, and sleep better ...

You and the referenced thread are quite correct that the RP2050 is a curate's egg : the 5V tollerance being conditional on Vddio at 3v3. Some real translators do not have this limitation, eg 74LVC. However, some do, eg 74LV1T is only "good" unpowered to 4v5 input (GEfGW ?). The RP2050 lacks the note which TI commonly append that going overvoltage on an (unpowered) pin is OK iff the current limits are observed. Whether this trade is available on the RP2050 is an interesting question. A common aproach is to fit series resistors as crude current limiters, 100R 1k 10k say. I shall observe that this thread neatly illustrates how building test instrumentation out of inexpensive components is not so easy, and that emanuel stiebler's observation that a good nights rest is best assured by using "real" voltage translators has merit. And, as you observe the reason for discussing the RP2050 and these issues here is the construction of adjuncts to old hardware. In new hardware you would have power sequencing and reset nets to control the low voltage to higher voltage power sequencing, reset release and shutdown arrangements. Martin -----Original Message----- From: Jay Logue via cctalk [mailto:cctalk@classiccmp.org] Sent: 30 July 2025 22:59 To: cctalk(a)classiccmp.org Cc: Jay Logue &lt;jay-cctalk0092(a)toaster.com&gt; Subject: [cctalk] Re: RP2350 5V Input Tollerant Pins I have not studied the RP2350 datasheet closely (and I'm definitely not an EE), but as I understand it, the caveat here is that 5V tolerance only exists while the device is fully powered (IOVDD at 3V3).  At lower supply voltages (e.g. during startup), digital I/O pins may be damaged by voltages higher than 3.3. The topic is discussed in more depth here, and in linked threads: https://forums.raspberrypi.com/viewtopic.php?t=375118 To bring this somewhat back around to cctalk, I faced this issue when designing my console adapter for the PDP-11/05 (github <https://github.com/jaylogue/pdp1105-console-adapter-v2>). It is based on the  rPI Pico (RP2040), which has a similar limitation.  I wanted the device to be able to be powered from the 11/05 itself.  But at power on, the supply voltage races with the SERIAL OUT (TTL) line, and always looses due to the time it takes for the onboard 3V3 regulator to stabilize.  Since I cared more about simplicity than power efficiency or speed, I went with a simple voltage divider rather than a level shifter. --Jay On 7/30/25 07:04, Martin Bishop via cctalk wrote: