The current scaling numbers are in many ways marketing numbers rather than a reflection
of the geometric realities of earlier decades. Early on a single geometry increment would
apply more or less to most of the chip. That's no longer true. So to the extent that
2 nm geometry appears at all, it's only in one or a few layers, with most layers
having significantly larger geometry.
Nevertheless, those numbers are still mindboggling. Especially when you consider the
machine (the EUV stepper) that has to project those patterns at that resolution onto the
wafer, at high speed. The fact that it's possible at all is just amazing; the fact
that only one company in the world is capable of doing it isn't much of a surprise.
I saw a video about that technology which said that it's analogous to shooting at a
dime on the moon, from earth, and asking "which side of the dime do you want me to
hit?" I think that's a slight exaggeration, but hitting WIlilam Tell's apple
on the moon, from earth, seems accurate enough. Yowza.
The big problem at those tiny geometries is that devices are small enough that quantum
mechanics is a major source of trouble. For example, insulators that small aren't
really insulators.
paul
On Jul 8, 2026, at 8:41 PM, Murray McCullough via
cctalk <cctalk(a)classiccmp.org> wrote:
We can stand in awe as classic computerists at the advancement of
technology: I recently read that chip technology size is at 2 nanometers
for ultra-large scale processors. In 1971 it was 10,000 nanometers or 10
microns. This is a 5000x reduction in size in 55 years. One has to ask: Is
Moore’s Law still alive?
Happy computing?
Murray :-)