On Mar 29, 2025, at 13:06, Milo Velimirović via cctalk <cctalk(a)classiccmp.org> wrote:  Try this one: https://hampage.hu/dr/unibus.html The “dual Standard pinout” for slots A/B was generally used for a BC11-A Unibus cable, with a Unibus terminator in the very last slot. The Unibus cable carried signals (not power!) between backplanes. Quad SPC is common to (at least) Modified Unibus(MUD) and Standard Unibus. The differences between the two backplane specs are in slots A/B only, with slots C-F the same (AFAIK.) Also some slots of the of the VAX730 backplane. Probably due to changes in cabinets and packaging. The 11/20 was unique in having a quad backplane mounted from side to side in a BA-11 (and upside-down too!) Most of the subsequent Unibus pdp11s had hex backplanes mounted either vertically, top to bottom, (11/40, 11/45 and 11/70,) horizonatlly, front to back, (some 11/05s, 11/34, 11/35, 11/44 etc.), another orientation was vertically to one side, front to back in 5.25” cabinets. EUB was unique to the 11/24 and 11/44 and only for memory boards. [https://gunkies.org/wiki/Extended_UNIBUS] The ability to use larger printed circuit boards; it gets you higher density and avoids the need to run (as many) interconnects off the board and thru the backplane. Remember that 50-60 years ago was the era of 14,16-pin DIP packages for small-scale and medium-scale integration; larger packages existed of course, but they were the exception. You still needed lots of wires to interconnect functionality between chip packages. Using a hex board instead of single or dual boards allowed many of those “wires” to be traces on a PCB, rather than run through the backplane or on an over-the-top jumper. (See the 11/34a.) See the Unibone, to ensure you’re not reinventing the wheel. It also includes a Unibus description that might be helpful. For something simpler take a look at the M1710 Unibus Interface Foundation Module. Brochure: https://vt100.net/manx/details/1,22302 https://retrocmp.com/projects/unibone —Milo

On Mar 29, 2025, at 12:33 PM, shadoooo via cctalk <cctalk(a)classiccmp.org> wrote: Hello, I'm searching information about all existing variants of DEC Unibus in Dual/Quad/Hex flavors. I read the "UnibusSpec1979.pdf" on bitsavers, which reports a "Standard Unibus" pinout in the last pages. However in several backplanes "Small Peripheral Controller", "Modified Unibus Device" and "Extended Unibus" are supported. Maybe also other unlisted Unibus variants do exist (e.g VAX 11/730)? I also found the gunkies.org WIKI very helpful, however it is still quite difficult to compare the pinout differences (dummy proof).

Where could I find a specific DEC documentation about the more recent variants, similar to the 1979 specs, but referred to SPC, MUD, EUB, ect? Big doubts: - why DEC, having defined the dual Standard pinout, had then to implement the quad SPC backplanes?

- why DEC, having defined quad backplanes, had then to implement the hex (standard + SPC) or (MUD + SPC) or EUB?

I mean: given that in AB all Unibus signals are present (from specifications), what is the need for CDEF?

Provided that several signals are duplicated in hex pinout, the backplane will connect homologue signals together, or AB bus will always be separated from CDEF bus? My aim is to design a reprogrammable digital logic board which could be employed in any system, using 18bits address or also 22bits (i.e. for 11/24).

The why not use a UniBone comment has merit, what will your (FPGA) implementation add ?

If you solve the (near) unobtanium OC driver / receiver problem - I for one will be all ears

https://forum.vcfed.org/index.php?threads/unibus-qbus-alternative-driver-ch… Found on my travels - should have been attached to my previous eMail My summary is "no easy answer" Martin -----Original Message----- From: Martin Bishop via cctalk [mailto:cctalk@classiccmp.org] Sent: 30 March 2025 22:44 To: General Discussion: On-Topic and Off-Topic Posts < cctalk(a)classiccmp.org&gt; Cc: Martin Bishop &lt;mjd.bishop(a)emeritus-solutions.com&gt; Subject: [cctalk] Re: DEC bus transceivers (was: DEC Unibus variants) David You will have seen my response to shadooo / Andreas. Occasional NOS in small quantities excepted, I'm also unaware of slow transition rate drivers available for purchase. The DS8641 DS3662 DS 3682 are to my knowledge all unobtanium. Your driver design sketches and comments are substantially on the money. Thank you for making them public. However, an effective implementation in discrete components would not be "tiny" - even with 0402 passives and a pick / place machine on the case. Perhaps someday, someone will do a Q/U driver on a multi project wafer - or is that unafordable. Or, to fly another kite - what about FPAA (Field Programmable Analog Array) components ? Regarding comparators, as receivers, the TLV3501 (for example) is a 5v / 5 ns part - add hysteresis and set the H/L thresholds using resistors. Certainly receives OC signals for me. Should you make further progress very interested to hear of it Best Regards Martin -----Original Message----- From: David Bridgham via cctalk [mailto:cctalk@classiccmp.org] Sent: 30 March 2025 14:59 To: Martin Bishop via cctalk &lt;cctalk(a)classiccmp.org&gt; Cc: David Bridgham &lt;dab(a)froghouse.org&gt; Subject: [cctalk] DEC bus transceivers (was: DEC Unibus variants) On 3/29/25 7:29 PM, Martin Bishop via cctalk wrote: implementation add ? I'm not shadoooo but I've also been working on a somewhat similar FPGA-based board called the USIC / QSIC. We started working on it before the UniBone but have been slower to come to completion. A lot slower. Maybe there's no point to it anymore but I keep poking along on the design anyway. Ah, yeah, this problem. At one point in the QSIC project I started doodling up circuits to deal with this so we wouldn't have to use up NOS bus transceivers, wouldn't have to deal with the 5V/3.3V conversion for the FPGA, and would be all surface-mount parts to make automated fabrication easier (I never found any DS3662s). A comparator for the receiver with just the right amount of hysteresis. Have to look around a little to find one that's fast enough to meet the 35 ns requirement but they're out there. And then the driver is just a transistor and a capacitor on the gate/base to limit the slew rate. Shouldn't be all that hard to design, right? Might want to go with a constant current source to charge/discharge that capacitor to make it a proper trapezoid waveform though I don't know that that's really needed. This all needs testing and I was going to make up a little test board with both my circuit and a DS8641 that could be plugged into different busses to have a look at the waveforms that come out. I looked up the pinouts for SPC, MUD, and QBUS so I could design a board that would equally work in all three. I was talked out of this idea though. We were doing enough new already with the whole rest of the board and from our prototype QSIC we knew that the DS8641s with level converters would work so it made sense to stick with that. Still, I think about this idea from time to time. In the small chance that anyone is interested, I just now threw my circuit ideas up on GitHub. Remember, this is doodling. I can see three generations of ideas in there, as I thought through different possibilities. I also had this idea about switchable, active termination so that's in there too, though I'm now less sure that's a good idea. https://github.com/dabridgham/DEC-Bus-Transceiver Dave

Your driver design sketches and comments are substantially on the money. Thank you for making them public. However, an effective implementation in discrete components would not be "tiny" - even with 0402 passives and a pick / place machine on the case.

Perhaps someday, someone will do a Q/U driver on a multi project wafer - or is that unafordable. Or, to fly another kite - what about FPAA (Field Programmable Analog Array) components ?

Regarding comparators, as receivers, the TLV3501 (for example) is a 5v / 5 ns part - add hysteresis and set the H/L thresholds using resistors. Certainly receives OC signals for me.

Should you make further progress very interested to hear of it

Does anyone have a list of what boards they were used on? I do have some boards I'm planning or recycling (I know, I shouldn't say that, especially here, but most are common boards nobody uses anymore.) I haven't looked at the IPBs yet, but did plan on pulling some of the chips. On Sun, Mar 30, 2025 at 9:59 AM David Bridgham via cctalk < cctalk(a)classiccmp.org&gt; wrote: > On 3/29/25 7:29 PM, Martin Bishop via cctalk wrote: > > The why not use a UniBone comment has merit, what will your (FPGA) > implementation add ? > > > I'm not shadoooo but I've also been working on a somewhat similar > FPGA-based board called the USIC / QSIC. We started working on it > before the UniBone but have been slower to come to completion. A lot > slower. Maybe there's no point to it anymore but I keep poking along on > the design anyway. > > > > If you solve the (near) unobtanium OC driver / receiver problem - I for > one will be all ears > > > Ah, yeah, this problem. At one point in the QSIC project I started > doodling up circuits to deal with this so we wouldn't have to use up NOS > bus transceivers, wouldn't have to deal with the 5V/3.3V conversion for > the FPGA, and would be all surface-mount parts to make automated > fabrication easier (I never found any DS3662s). A comparator for the > receiver with just the right amount of hysteresis. Have to look around > a little to find one that's fast enough to meet the 35 ns requirement > but they're out there. And then the driver is just a transistor and a > capacitor on the gate/base to limit the slew rate. Shouldn't be all > that hard to design, right? Might want to go with a constant current > source to charge/discharge that capacitor to make it a proper trapezoid > waveform though I don't know that that's really needed. > > This all needs testing and I was going to make up a little test board > with both my circuit and a DS8641 that could be plugged into different > busses to have a look at the waveforms that come out. I looked up the > pinouts for SPC, MUD, and QBUS so I could design a board that would > equally work in all three. > > I was talked out of this idea though. We were doing enough new already > with the whole rest of the board and from our prototype QSIC we knew > that the DS8641s with level converters would work so it made sense to > stick with that. > > Still, I think about this idea from time to time. In the small chance > that anyone is interested, I just now threw my circuit ideas up on > GitHub. Remember, this is doodling. I can see three generations of > ideas in there, as I thought through different possibilities. I also > had this idea about switchable, active termination so that's in there > too, though I'm now less sure that's a good idea. > > https://github.com/dabridgham/DEC-Bus-Transceiver > > Dave > >

In the "old" days, such as the 1970's, pretty much any DEC-manufactured peripheral was supplied as a bunch of cards that plugged into a specific backplane section, generally 9 slots, I think. A couple double-wide slots were for the Unibus in and out connectors.

On Sat, Mar 29, 2025 at 9:46 PM Jon Elson via cctalk &lt;cctalk(a)classiccmp.org&gt; wrote: There were plenty of 9-slot system unit peripherals, but there were also 4-slot system unit peripherals in the early days.

On Sun, Mar 30, 2025 at 11:06 AM Jon Elson wrote: I also remembered a couple other 4-slot system unit peripherals I have: RK11-D VT11 Probably the most common 9-slot system unit devices I've encountered are: RK611 (which happens to have a couple of available SPC slots) DH11 RH11 But there are many of both sizes. Cheers, -ethan