30 Jul
2025
30 Jul
'25
6:57 p.m.
I have successfully used a 74LVC1G34DBV to do exactly that, 5V supply, 10u & 100n on
the supply, 499R in series on the output, driven from 3v3 LVTTL.
Run at 5V the WS2812B has Vil/Vih of 0.9 and 3.5 V. Hence you need more than LVTTL or TTL
logic levels. I would be surprised if a pull up was a good solution, at 800 kHz you wish
transition times on the order of 75 ns : PU dissipation ?
The essential spec for a WS2812 buffer / driver device is TTL input levels, 5V CMOS output
levels : the usu suspects are 74LVC and 74HCT
Martin
-----Original Message-----
From: Adrian Godwin [mailto:artgodwin@gmail.com]
Sent: 30 July 2025 22:29
To: Martin Bishop <mjd.bishop(a)emeritus-solutions.com>
Cc: General Discussion: On-Topic and Off-Topic Posts <cctalk(a)classiccmp.org>rg>; Paul
Koning <paulkoning(a)comcast.net>
Subject: Re: [cctalk] Re: RP2350 5V Input Tollerant Pins
I was thinking specifically of ws2812 addressable leds which have CMOS levels. The data
stream is fairly slow (~800kHz) and can usually be generated from 3v3 with the common FET
voltage shifter (which also has passive pullup). It's sometimes driven with 3v3 but is
marginal. I was thinking that it might be driven bye a 2350 with a 5V pullup more
reliably.
On Wed, Jul 30, 2025 at 11:19 PM Martin Bishop <mjd.bishop(a)emeritus-solutions.com>
wrote:
Adrian
The summary answer to your questions must be "in general no" : 5V CMOS levels
are quite different from TTL levels and open drain /collector signalling is inherently
slow.
5V CMOS, with its very high Vih (typ > 3.5V), is one of those things it is nice not to
have to work with. If you do have to drive it then, in general, logic (level) translation
families are necessary.
Contrariwise, 3v3 LVTTL and 5V TTL thresholds are essentially equal Vil at 0v8 and Vih at
2V. However, 5V pull ups and transients make 5V --> 3v3 connections an invitation to
smoking : YMMV.
If you have a specific interfacing problem, the essential information to select a way
ahead is source chip, sink chip, signal speed, and constraints.
The can being kicked in this thread was the RP2050's 5V tollerant input, which should
make it useable for direct connection to TTL, then some apparent "documentation"
issues were identified ...
Some "handy primers" are:
https://www.ti.com/lit/pdf/sdyu001?keyMatch=logic%20families&tisearch=
universal_search see page 4 for typ logic levels
https://www.ti.com/lit/pdf/ssztc76?keyMatch=logic%20families&tisearch=
universal_search
https://www.ti.com/lit/pdf/scyt129?keyMatch=little%20logic&tisearch=un
iversal_search
https://www.ti.com/lit/pdf/scyb018?keyMatch=voltage%20level%20translat
ion%20guide&tisearch=universal_search
Martin
-----Original Message-----
From: Adrian Godwin [mailto:artgodwin@gmail.com]
Sent: 30 July 2025 21:33
To: General Discussion: On-Topic and Off-Topic Posts
<cctalk(a)classiccmp.org>
Cc: Martin Bishop <mjd.bishop(a)emeritus-solutions.com>om>; Paul Koning
<paulkoning(a)comcast.net>
Subject: Re: [cctalk] Re: RP2350 5V Input Tollerant Pins
What about output pins in open-drain mode with a 5V pullup ? Can they provide a 5V
CMOS-compatible output ?
On Wed, Jul 30, 2025 at 9:40 PM Paul Koning via cctalk <cctalk(a)classiccmp.org>
wrote:
>
>
>
> > On Jul 30, 2025, at 3:07 PM, Martin Bishop
<mjd.bishop(a)emeritus-solutions.com> wrote:
> >
> > https://www.eenewseurope.com/en/raspberry-pi-spins-its-rp2350-adds-5v-suppo…
was my point of departure, doubtless a recycled press release.
>
> Yikes. Assuming that is accurate, Raspberry Pi screwed up very severely by claiming
5V support in the data sheet without saying it only applies to the A4 rev. Any number of
people will fry their chips because of this blunder.
>
> paul