14 Mar
2025
14 Mar
'25
8:14 a.m.
Paul
Prompted by your mention of this thesis a month ago - I went in search
The entire thesis appears to be available in pdf
https://www.cwi.nl/en/news/new-insights-from-reconstructing-the-first-algol…
https://ir.cwi.nl/pub/28427/
Martin
-----Original Message-----
From: Paul Koning via cctalk [mailto:cctalk@classiccmp.org]
Sent: 14 March 2025 00:02
To: cctalk(a)classiccmp.org
Cc: Paul Koning <paulkoning(a)comcast.net>
Subject: [cctalk] Re: IDT 49C402BG84 Pinout?
On Mar 13, 2025, at 7:56 PM, Paul Koning via cctalk
<cctalk(a)classiccmp.org> wrote:
An additional comment on that. To understand any field well, it is generally helpful, and
at times crucial, to have some knowledge of early work. I just read a translation of some
of the works of Galileo that makes that point in so many words in the introduction.
Similarly, while people don't build compilers today the way they did in 1960, it is
still valuable to read how Dijkstra and Zonneveld wrote the first ALGOL-60 compiler and,
along the way, had to invent many of the compiler construction techniques that were later
routinely taught and used in university compiler construction courses. There's an
outstanding analysis of that, in the Ph.D. thesis of Gauthier van den Hove. (It's not
yet a published document; I think that has something to do with copyright and publication
practices at some universities, perhaps Dutch or European conventions.) He subtitled his
thesis "New insights from old programs".
paul
On Mar 13, 2025, at 4:35 PM, ben via cctalk
<cctalk(a)classiccmp.org> wrote:
On 2025-03-13 1:36 p.m., Paul Koning via cctalk wrote:
To understand fully how the 6000 machines work, ...
Depends on which one. RTL was 3.6 volts
positive, as far as I can remember. I actually have a keyboard that has some of those
devices in it. Yes, ECL is around 3 volts also but negative supply. And of course some
people designed systems with positive supplies but "negative" logic, in the
sense that ~0 volts is logic 1 while near-VCC is logic 0; the CDC 6000 series machines are
an example.
I was thinking of the PDP-8 there. 0 Volts logic 1 -3 volts logic 0.
FPGAs come in amazing sizes if you have
sufficient money. I hope some day to cram an entire CDC 6600 into an FPGA. The main
problem with this isn't FPGA sizes (by today's standards, an upper-midrange FPGA
can do the job, memory included) but rather the creation of an accurate model given the
bizarre and hairy timing of that machine. I have a gate level model, but it doesn't
work yet because of those issues.
What would the purpose of said computer be?
Might be better off with a clean 64 bit design and 16 bit bitslices.