David
You will have seen my response to shadooo / Andreas.
Occasional NOS in small quantities excepted, I'm also unaware of slow transition rate
drivers available for purchase. The DS8641 DS3662 DS 3682 are to my knowledge all
unobtanium.
Your driver design sketches and comments are substantially on the money. Thank you for
making them public. However, an effective implementation in discrete components would not
be "tiny" - even with 0402 passives and a pick / place machine on the case.
Perhaps someday, someone will do a Q/U driver on a multi project wafer - or is that
unafordable. Or, to fly another kite - what about FPAA (Field Programmable Analog Array)
components ?
Regarding comparators, as receivers, the TLV3501 (for example) is a 5v / 5 ns part - add
hysteresis and set the H/L thresholds using resistors. Certainly receives OC signals for
me.
Should you make further progress very interested to hear of it
Best Regards
Martin
-----Original Message-----
From: David Bridgham via cctalk [mailto:cctalk@classiccmp.org]
Sent: 30 March 2025 14:59
To: Martin Bishop via cctalk <cctalk(a)classiccmp.org>
Cc: David Bridgham <dab(a)froghouse.org>
Subject: [cctalk] DEC bus transceivers (was: DEC Unibus variants)
On 3/29/25 7:29 PM, Martin Bishop via cctalk wrote:
The why not use a UniBone comment has merit, what will
your (FPGA) implementation add ?
I'm not shadoooo but I've also been working on a somewhat similar FPGA-based board
called the USIC / QSIC. We started working on it before the UniBone but have been slower
to come to completion. A lot slower. Maybe there's no point to it anymore but I keep
poking along on the design anyway.
If you solve the (near) unobtanium OC driver /
receiver problem - I
for one will be all ears
Ah, yeah, this problem. At one point in the QSIC project I started doodling up circuits
to deal with this so we wouldn't have to use up NOS bus transceivers, wouldn't
have to deal with the 5V/3.3V conversion for the FPGA, and would be all surface-mount
parts to make automated fabrication easier (I never found any DS3662s). A comparator for
the receiver with just the right amount of hysteresis. Have to look around a little to
find one that's fast enough to meet the 35 ns requirement but they're out there.
And then the driver is just a transistor and a capacitor on the gate/base to limit the
slew rate. Shouldn't be all that hard to design, right? Might want to go with a
constant current source to charge/discharge that capacitor to make it a proper trapezoid
waveform though I don't know that that's really needed.
This all needs testing and I was going to make up a little test board with both my circuit
and a DS8641 that could be plugged into different busses to have a look at the waveforms
that come out. I looked up the pinouts for SPC, MUD, and QBUS so I could design a board
that would equally work in all three.
I was talked out of this idea though. We were doing enough new already with the whole
rest of the board and from our prototype QSIC we knew that the DS8641s with level
converters would work so it made sense to stick with that.
Still, I think about this idea from time to time. In the small chance that anyone is
interested, I just now threw my circuit ideas up on GitHub. Remember, this is doodling.
I can see three generations of ideas in there, as I thought through different
possibilities. I also had this idea about switchable, active termination so that's in
there too, though I'm now less sure that's a good idea.
https://github.com/dabridgham/DEC-Bus-Transceiver
Dave