Your caveat that the data sheet requires careful study is completely correct. Also, the
5V tollerance applies to the A4 revision, date codes / top marks will also require
scrutiny. I would suspect that A4 2050's are not yet "on the streets".
FWIW my low tech TTL --> LVTTL input interface design is a 3v0 Zenner clamp
Martin
-----Original Message-----
From: Paul Koning via cctalk [mailto:cctalk@classiccmp.org]
Sent: 30 July 2025 16:46
To: cctalk(a)classiccmp.org
Cc: Paul Koning <paulkoning(a)comcast.net>
Subject: [cctalk] Re: RP2350 5V Input Tollerant Pins
There's a small detail that's in the document: some of the GPIO pins double as
analog inputs (for the ADC). Those, unlike the other GPIO (digital only) pins, are not 5
volt tolerant. Four of the GPIO pins brought out to the edge of the Raspberry Pico board
are those analog/digital combo pins, so for any 5 volt work you'd have to avoid
directly connecting 5 volt devices.
paul
On Jul 30, 2025, at 12:30 PM, Paul Koning via cctalk
<cctalk(a)classiccmp.org> wrote:
That's interesting. I have been using the RP2350 for a while now but I missed that
detail.
For what I do, I've found that just a voltage divider works fine for 3 volt tolerant
inputs with 5 volt drive. And 5 volt TTL seems to be happy with the 3 volt logic high
that the Pico chips produce. So while voltage shifters are well known I haven't found
the need for them.
Still this is handy to know.
The RP2350 is quite an amazing chip for very little money. A dollar or two more than the
RP2040, which itself is already highly capable. By the way, there is a very nice FORTH
system for these called Zeptoforth; I've been doing a bunch of work with that.
paul
On Jul 30, 2025, at 10:04 AM, Martin Bishop via
cctalk <cctalk(a)classiccmp.org> wrote:
https://www.raspberrypi.com/products/rp2350/
From postings, I know that folks use the RP2350 for interfacing; the trade press has been
shipping news of RP's rev A4 datasheet in volume.
The datasheet should tell all. However, the 5V tollerance of the "IO" pins is
significant for its simplification of TTL interfacing; the maximum supply and output
voltage remains 3v3. See section 14.8.2 (p 1335) et seq - NB the FT indication.
Martin