Really long shot, and I have asked here before without much luck, but anyone
have a copy of the Compaq System Manager Facility 1.10 or 1.11 (or any
version for that matter). This would have been released in 1994/95 time
frame and is necessary for the use of the Compaq Server Manager/R EISA
board. This is a very early EISA RILO board for the System Pro and Proliant
line of servers. Please note this is not the same as the System Management
Agents nor the Insight Manager. TIA!
-Ali
Hi everyone,
I recently dug out my V880 and all seems to be working brilliantly. I've always liked these machines and it would be nice to upgrade this to the V880z spec, ie by adding the mighty
XVR-4000 graphics module.
I know the XVR-4000 is a bit of a mixed bag, but would be fun to play around with this and also who can not be impressed with the shear size of the module. Must be one of the biggest Sun graphics 'cards'?
Does anyone have one of these boards they would be willing to part with. Happy to pay a reasonable amount as I know these are not easy to find.
PM me if you have anything.
Ian.
Over the past couple of months I have been working on my FPGA
implementation of the IBM 1410 1960's era pre System/360 system again.
I am pleased to share that the CPU now passes a significant diagnostic,
CU01, which tests almost all of the instructions, and also tests I/O
with overlap and the priority feature (interrupts). Also, it runs at
generally the same speed as the original machine (comparing the IBM
estimates for 1000 passes), using the same logic as the original machine
(though no doubt optimized by the process of taking in VHDL logic
statements and turning combinatorial logic into lookup tables (LUTs),
and some additions of "D" flip flops to avoid race conditions in latches
and logic loops.)
(The speed is the same because its "oscillator" - crystal controlled in
the original - is now a clock divider/counter off of the FPGA chip clock.)
For more details, see
https://www.computercollection.net/index.php/ibm-1410-fpga-implementation/
Mostly the ALD (Automated Logic Diagram) data capture seems to have been
very accurate. I really only had to do four things this year to get it
to this point:
- Make the necessary logic gate deletions / changes for configuration
option S40/$40 - 40K of core
- Add the ability to transfer a core image from the PC support program
to the FPGA.
- Fix some issues in the Assembly Channel because while almost all of
the ALDs are for a 1410 with the Accelerator feature, several pages of
the very important Assembly channel were for the base 1410 model.
- Deal with a race condition during overlapped I/O
These are generally discussed in individual blog posts off the above link.
I really was quite happily surprised that when capturing the data on
over two hundred ALDs with over 10,000 logic gates, over 4,200
individual unique signals, more than 12,000 signal names on individual
ALDs, and more than 32,000 interconnections that there were not a lot
more problems than these. (I may run into some as yet undiscovered
errors involving the channels as I add I/O devices, though).
I suppose that there were not more problems because for most of the
individual sheets and in many cases groups of sheets I wrote VHDL test
benches using the Intermediate Logic Diagrams (ILDs) as a guide, and of
course took considerable care during the data entry process from the
ALDs, checking connection counts on each logic block, for example.
The last post ("Off to the Races") on the aforementioned web page also
discusses the next expected steps: some more work on the PC/Console
support program, more diagnostic tests, other support program
enhancements, and figuring out how to go about I/O, especially since I
don't have ALDs for the 1414 I/O Synchronizers.
But I no longer have any doubts about the viability of this process, so
long as the FPGA logic clock is somewhere around 10x the logic clock of
the simulated machine. (I expect to try and "push it" by speeding up
the 1410 logic clock to see at what ratio of the FPGA clock to the CPU
clock things break down, as well).
JRJ
I have a PDP-11/53 and have just started playing with an AAV11-C D/A
board. It is a 4 channel D/A convertor with 12 bit resolution.
Can it be used to play an audio bit stream?
Here is simple code used to see if the thing was actually working:
.title AAV11 D/A test
;
.asect
dbr0 = 170440
.=1000
start:
mov #7777,r0 4096 value to R0
mov #dbr0,r1 first D/A buffer out
loop: mov r0,(r1) transfer value in r0 to D/A out
dec r0 subtract 1 from D/A value
bne loop
br start loop back to start
I was surprised to see that it took ~34 ms to run through all the
numbers from 0-7777, that is about 34 Hz. The manual says the 'settling
time' is 6 microseconds. Is this fast enough for audio?
How would you convert a modern audio file into 12 bit integers?
Doug
A friend suggested that some in this group may have an interest in this.
ruos stands for Retro Useless Operating System
ruos is an OS for the long-obsolete PDP11/70 from Digital Equipment Corporation. ruos runs on the simh simulator for that machine. It was written completely from scratch in C and assembler. On a modern machine, the kernel and user code builds in a few seconds.
Overview:
It can run something less than 64 processes simultaneously with one user on the console and others on other serial ports. Equal priority CPU-bound tasks share the CPU.
The user program API includes a number of stdio-like C functions
ruos was built using the gcc toolchain for the PDP11 (Thanks for those toolchain bug fixes Paul Koning!)
Each user process is given exactly 64kB for code, data, heap, and stack and is (mostly) isolated from other processes
Users access the OS using a very simple unix-like shell for command execution with pipes allowed
It does not have its own file system but uses a proxy for file IO. The proxy code (Python 3) is included.
Communication between the OS and the proxy is via UDP/IPv4/Ethernet.
Familiar user binaries include: cat, ps, echo, grep. Device status is provided by ds
If a user tries to run a program that is not native to ruos, an attempt is made to run it on the proxy. Using this mechanism, users can edit files or build new programs (assuming the gcc toolchain is installed on the proxy and the proxy is on the same machine as simh).
It is accessible here:
https://ajco...@bitbucket.org/ajcorbeil/ruos.git <https://ajcorbeil@bitbucket.org/ajcorbeil/ruos.git>
Regards,
Alan Kirby
Just got the following message in the account that I use to receive
cctalk email:
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FYI
Chuck
Hello sir,
I used to get your newsletter but no longer...I understand there are
problems...
I would be most interested in getting your newsletter again.
Many thanks,
Murray 🙂
I know this is off topic, but I think there are a number of hams here.
Looking to get back into it but have some questions.
Now that the a**holes have completely trashed all the USENET ham radio
groups where do hams go for the kinds of discussions that used to be there?
bill
Hi all,
maybe someone here is interested in the FOSBIC (FORTRAN Simulated BASIC Interpretive Compiler) system.
Background: This was developed, oder rather ported from UWBIC (University of Washington, Prog. W.H. Sharpe) in the mid 70s, by Prof Weber et al. at the German University of Gießen, for the purpose of teaching BASIC on their CDC3300 batch system.
It is written in FORTRAN IV, and knows most of Dartmouth BASIC, including MAT statements and basic sequential/ISAM file handling.
I have ported that, with the help to GNU gfortran, to modern Windows (mingw/cygwin) and Linux, so anyone may play with it. It is still a batch system, i.e. on has to provide the BASIC program as a file (formerly it had to be a card deck), and feed it into the program through stdin, as
in "./fosbic < hello.bas | ./asa"
The code with many examples is available at https://github.com/hveit01/FOSBIC, and has also found its way to bitsavers.org/pdf/uni-giessen.
--
Regards
Holger
