PDP 11/24 - A Step Backwards

[Noel Chiappa]

    > It was quite a struggle to separate those nylon connectors, is there a
    > trick to it?

You mean the Mate-n-lok's? Not really; just make sure the catch is released.

What did you do about DCLO? (Oh, I think I see the answer, below.... looks
like you're relying on the pullup on K3...)

    > When I powered on, the CPU LEDs did not light up.

Two of them ('0' and '1') are just bits in a special register, and thus only
do anything when the bootstrap code fondles them. When you get ODT running,
you can amuse yourself turning them off and on manually! :-)

    > I did notice that the CLK LED flickered on briefly when I powered it
    > off.

Interesting. Not sure exactly what we can deduce from that; but interesting.

    > I put a scope probe on TP1 (p152 of the PDF), there was no activity,
    > the pin remained high.

Yes; the signal there (MCLK H) is more or less the same one that drives the
'CLK' LED (MCLK L); so no big surprise there. Still, that reduces the problem
space to a small part of K1. 

    > The problem now is that I expect I will need to probe various pins to
    > find out what is going on. But I don't have a Unibus extender and I am
    > reluctant to remove the backplane. From what I can tell in the
    > Technical Manual you can't install the CPU in other slots

Basically right; the backplane and CPU are designed to have it go in slot 1.
It _might_ work in other MUD slots, with some loss of functionality (e.g.
slot 2 doesn't have grant lines; MUD slots won't have the 'UNIBUS Map board
pesent' line - pin FE1, on K11, UB TO MA VIA UBMAP) but I wouldn't want to
chance it, there might be a clash.

    > I am forced to tack solder probe wires to the chips, which works but is
    > time consuming. Any other ways?

Sorry, I don't have any experience to suggest any; too well supplied with
extender cards, so I've never had to resort to alternatives!


    > I *think* I have found something. There could be a fault in E52 (sheet
    > K6, p157 of the PDF). While K6 BUS DCLO L is +5V, I am measuring K6 BUF
    > DCLO H at an average 1.64V

Yeah, that's wrong. E52 is bad, and will have to be replaced.

(From the +5V on BUS DCLO, I guess you're relying on the pullup? DCLO on the
UNIBUS, with the resistor network on the M9302, should be about 3.5V - but now
I'm confused, even with the P/S connector unplugged, it should still be 3.5V
or so. Oh well, it's late, the brain is powering down... :-)

The 'unused' gate in E52 is the one that the added wires from the ACLO ECO went to;
I wonder if it was damaged by the -15V, somehow?

    > logical 0 output should be 0.4V max

Which is what you should be seeing.

    > I also measured K6 BUF DCLO L to be always low, suggesting it thinks
    > the K6 BUF DCLO H is a logical 1.

Yup; and that definitely explains why the clock isn't running - BUF DCLO L is
clearing E41 on K1.

Anyway, you'll have to replace E52 (which will be a bit of a pain, with the 3
ECO eires tacked to it). The DS8641 is an old chip, no longer in production, so
the usual suppliers may not have it, but there are some on eBait.

	Noel