MSV11-J engineering info

[Glen Slick]

On Mon, Jul 2, 2018 at 7:14 PM, Noel Chiappa via cctalk
<cctalk at classiccmp.org> wrote:
> Hi, I'm looking for engineering info on the MSV11-J. I was unable to find any
> prints online, or even a technical manual. (I have the User Manual, but it doesn't
> have much detail.)

> The main issue I'm after is working out which bits go into which chips.  I
> have some other QBUS memory boards with no documentation where I created the
> mapping by just pulling chips, e.g.:

> I'm not sure it's going to be possible to work it out from looking at board
> traces, since the MSV11-J is ECC memory, and I expect all the data lines just
> disappear into the two huge gate array chips.
>

There are 88 41256 256Kx1 DRAMs on a 2MB MSV11-J. Each 512KB bank has
22 256Kx1 DRAMs organized as 16 data bits plus 6 ECC bits.

If someone was sufficiently motivated I suppose they could probe each
of the 88 DRAMs while writing various bit patterns of data to various
memory locations and work out the mapping that way. From a brief look
at the manual it might be possible to use diagnostic modes to write
specific ECC bit patterns and work out the ECC bit mappings as well.
Might be very tedious, so might need lots of motivation.

I'm not sure which would be more work, probing one or a small number
of DRAMs at a time, or hooking up an old school large channel count
logic analyzer to probe all 88 DRAMs at the same time. (You can get
around 200 data channels with a couple of HP 16550A modules or three
HP 16555A modules in an HP 16500 or 16700 series mainframe).

If I ever get really bored some day maybe I'd take a look and try to
see just how tedious it might be.