Qbus split I&D?

[Paul Koning]

> On Mar 18, 2015, at 9:45 AM, Johnny Billquist <bqt at update.uu.se> wrote:
> 
> On 2015-03-17 22:45, John Wilson wrote:
>> But thinking about how it must work hurts my head.  It's emulating Unibus
>> memory at the same time that it's emulating the Unibus map -- i.e. CPU
>> accesses (which should be relocated through the onboard PARs) are coming
>> over the same bus as DMA (which should be relocated using the Unibus Map).
>> How does it know which is which?  Does it need to tap into each model of
>> CPU somehow (like how a Microverter gets at MMR3)?  Or is it something
>> simple like, BBSY is never asserted by the CPU (not obvious from docs --
>> the CPU doesn't need to negotiate to become a master but it still is one
>> when it's accessing memory) so if it's on, this is DMA?  And what if there's
>> a cache, like the KK11A, that doesn't know about the outboard PARs?
> 
> Not sure it's that hard. On the bus, I believe it is visible if this is an NPR transaction or not. The Unibus map only applies to NPR transactions.
> 
> Addresses originating from the CPU should get the full 22 bit address from the MMU.

Yes, but the Unibus map is still involved; if the CPU generates an address in the range 17000000 to 17577777, it lands on the Unibus and is then mapped by the Unibus map.  More precisely, it works that way for 11/44 and 11/70 — but not for the J-11.  That’s a difference not documented in the PDP-11 Architecture handbook model differences table; I ran into it while helping Sytse van Slooten debug an error message from RSTS/E on his VHDL PDP-11.

The reason I/O registers work is that the Unibus maps has 31 pages, not 32; it maps the Unibus addresses below the 4kW I/O range only.  

	paul