PDP-8 GTF question

[Vincent Slyngstad]

From: Brian L. Stuart: Monday, July 27, 2015 10:00 AM
>> I can see where this happens in the M837 schematic (E50), 
>> whenever DF is gated to AC9-11.  That, in turn, seems to 
>> be for GTF or RIB.
> 
> I wonder if there are differences in different versions of the
> schematics.  If I'm reading the versions I got from bitsavers
> correctly, on E50, Pins 2, 5, 11, and 14 are gated on to
> DATA3, 9, 10, and 11 by a low on Pin 9.  It looks like Pin 9
> does identify the RIB and GTF instructions.  But on this
> version, it looks like Pin 2 is pulled high through R8.  The
> interrupt inhibit signal does come into Pin 1 which is gated
> onto DATA3 by a low on Pin 7, and it's controlled by the
> Omnibus IND signals for getting info to the front panel.
> So it appears that these versions of the drawings agree
> with the maindec and the observed behavior rather than
> the documentation.
> 
> The versions I'm looking at appear to be for the Revs D
> and E.  Are the drawings you have that agree with the
> documentation for an earlier rev, perhaps?

My drawings are for version D on revision C etch, but they 
agree with yours on these connections.  I was misreading 
which signal went to pin 9 vs pin 7.

So it appears the KM8E does read a constant 0 for bit 3 
during GTF (and RIB).  This will apparently be different 
everywhere else (DECmates, KT8A, etc.).

BTW, my replies have been bouncing from the Yahoo 
groups, so you may want to forward stuff or otherwise 
keep those folks in the loop.

    Vince