It's time to restore the 11/45.

Jon Elson elson at
Thu Feb 5 11:43:25 CST 2015

On 02/05/2015 10:15 AM, Noel Chiappa wrote:
>      > From: Jacob Ritorto
>      > Can anyone understand and explain the unibus a / unibus b concept?
> I've never personally worked on a machine with them separate, but the picture
> on pg. 15 of the 11/45 Processor Handbook (1971 edition), and accompanying
> text, should make what's going on pretty clear.
> You have the 'normal' UNIBUS ("UNIBUS 1" they call it), controlled by the
> 11/45 CPU, on which regular memory, devices, etc live. The CPU also has
> access, via a special path (I guess this was later named "FASTBUS"?), to two
> _separate_ banks of high-speed memory. Those memories are _each_ dual ported;
> one port to the CPU's direct path, the other to a second UNIBUS, ("UNIBUS 2").
> So something on UNIBUS 2 could be talking to one bank of high-speed memory
> while the 11/45 CPU talks to the other bank - while at the same time, a DMA
> device on UNIBUS 1 could be talking to memory on UNIBUS 1. I.e. three
> separate memory transfers all going on _completely_ simultaneously.
> UNIBUS 2 does not have a 'bus master' - one has to be provided by plugging
> some PDP-11 into it. One can either plug another PDP-11 into UNIBUS 2
> (forming a primitive multi-processor, one in which the two machines share
> access to the high-speed memory on the 11/45); or one can 'jumper' the two
> UNIBI (is that the plural?) in the 11/45 together, at which point DMA devices
> on UNIBUS 1 can do DMA into the high-speed memories (which they do not have
> access to, if the two are separate).
Gee, our 11/45 (SN343) didn't have this, as far as I know.  
This sounds more like an


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