An IBM 1410 puzzlement...

Jay Jaeger cube1 at
Mon May 16 16:52:32 CDT 2022

I have a puzzlement with my IBM 1410 FPGA implementation.

ALD page, ILD figure 89

The symptom is this:  The CPU runs and can execute instructions. So, 
stuff is generally working.

Starting the address set process, the console appropriately prints the 
"B" prompt (to set the instruction address into the IAR, B means 
"BRANCH") or the "#" prompt to set other addresses.  Normal stops print 
the "S" as expected, errors print the "E" as expected and single cycle 
or I/E mode print the "C" as expected.

However, starting a display operation (to display memory), which ought 
to print a "D", prints an invalid parity "F" character - Bit 2 is picked 
when it should not be.  I have verified that "-S Special Char B" is 
active (active low)

I first saw this on real FPGA hardware, and then confirmed it / did some 
troubleshooting under simulation.

Here is what I found:

Looking at the ALD, a "D" is printed when
The Console Matrix at position 30 or 35

All of those conditions are satisfied.  Address Set is appropriately 
active because a display operation starts off by entering an address 
(even though I don't have console input implemented yet, that is not 
involved at this point).  And, indeed "-S SPECIAL CHAR D" is active 
(active low), as expected.

Looking at the ALD, a "B" is printed when
+ The console's address set select rotary switch is NORMAL (it is)
   (It will print '#' for other positions of this switch)
The Console Matrix at position 30 or 35

And, indeed, all of these conditions are satisfied as well, and indeed 
"-S SPECIAL CHAR B" is active (active low) as well.

The FE instructional materials confirm that ADDRESS SET ROUTINE should 
be active when starting a display operation, consistent with the ALD and 
the ILD - because both then proceed to allow the operator to input an 

So, this feels like a bug - an implementation error that was later 
corrected.  The ALD I have is pretty early - 6-15-1961, with just one 
ECO, and that ECO ("B") isn't on any of the gates on that ALD (this is 
not unusual), so this is probably essentially the original ALD.

The fix would be pretty easy: to include "+S DISPLAY ROUTINE" onto the 
wired or / "DOT" at coordinate 1B (to inhibit "B") and also to add a 
wired or / "DOT" with "+S DISPLAY ROUTINE" at the output of gate 2I.

In both cases, the signal "+S DISPLAY ROUTINE" would then inhibit the 
"B" or "#" (depending upon how the relevant switch is set.)

But I'm just really surprised at the whole thing.  Not really asking 
anyone to do anything, necessarily, but if anyone wants to confirm I'm 
not nuts (or demonstrate to me that I am nuts), feel free.

[I am also experiencing it printing a "." when the mode switch is in CE, 
which isn't right either - but haven't looked at that.  It should be 
printing a "#", regardless of the setting of the Address Entry switch - 
I won't be surprised if the same kind of thing is going on there, as 
this also involves the "address set routine" and matrix position 35 - 
and a "." is a "#" plus bits B and A - so the evidence is pretty strong 

The documents:

1415 Console CE:

ILD (see Figure 89, page 95 of the PDF below)  [ILDs read pretty much 
like modern logic diagrams]

The ALD (page 60 of the PDF below) [ALDs are tricker, because 
of "DOT-ted" connections, and the logic family (RTL NAND *mostly*).


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