Core memory

[Tom Hunter]

DEC PDP-8/e core memories have a combined Sense/Inhibit line.
There are only 3 wires through each core donut: X, Y, Sense/Inhibit.
The PDP-8/e core memory is very well described starting at page 3-60 of the
Maintenance Manual Volume 1:

http://www.bitsavers.org/pdf/dec/pdp8/pdp8e/DEC-8E-HMM1A-D-D_PDP-8e_Maintenance_Manual_Volume_1_Processor_Sep73.pdf

Tom Hunter

On Sun, Apr 3, 2022 at 7:04 AM Curious Marc via cctalk <
cctalk at classiccmp.org> wrote:

> You don’t strictly need an inhibit wire to write cores. You can write the
> core with just the addressing lines. The inhibit wire is just there to
> simplify the addressing electronics logic in early core memory, so you
> don’t need to have per core control of the current in the address lines
> when writing. You just do it wholesale: scan all address lines with current
> in one direction during reads, scan once again with current in the other
> direction during writes, with inhibit when needed.
>
> You could certainly use the sense wire as an inhibit. But that gets
> impractical with a diagonal weave, because you’d have to know in which
> direction the inhibit works and reverse the inhibit current accordingly.
> And it’s different for each core depending on the direction the sense wire
> crosses the core. So it defeats the purpose of simplifying the control
> logic with an inhibit wire. Therefore I don’t think that scheme is used.
>
> In practice, 3 wire systems that use the same wire for inhibit and sense
> (like some IBM core planes) have the sense go along the address lines, and
> use a half plane column shift to provide cancellation of the unwanted
> signal induced from the address line it is running along. We demonstrate
> such a 3 wire plane here: https://youtu.be/AwsInQLmjXc .
>
> So in your plane, the sense wire is likely just used for reads, and the
> writes are done uniquely with the address wires, like I demonstrate here:
> https://youtu.be/7ozNMgx7WtQ
>
> Marc
>
> > On Apr 1, 2022, at 2:14 PM, Brent Hilpert via cctalk <
> cctalk at classiccmp.org> wrote:
> >
> > On 2022-Apr-01, at 11:51 AM, Paul Koning wrote:
> >>>> On Apr 1, 2022, at 2:38 PM, Brent Hilpert via cctalk <
> cctalk at classiccmp.org> wrote:
> >>>> On 2022-Apr-01, at 6:02 AM, Paul Koning via cctalk wrote:
> >>>
> >>>> When I looked at that ebay listing of "glass memory" it pointed me to
> another item,https://www.ebay.com/itm/265623663142 -- described as "core
> rope memory".  Obviously it isn't -- it's conventional core RAM.
> Interestingly enough, it seems to be three-wire memory (no inhibit line
> that I can see).  It looks to be in decent shape.  No manufacturer marks,
> and "GC-6" doesn't ring any bells.
> >>>
> >>> Well, it would still work for 1-bit-wide words, so to speak. One
> wonders what the application was.
> >>
> >> I wonder if the sense wire was used as inhibit during write cycles --
> that seems doable.  It would make the core plane simpler at the expense of
> more complex electronics.  With that approach, you have regular memory, not
> limited to 1 bit words.
> >
> > Maybe I'm being overly cautious, but offhand I'm initially skeptical
> without doing the math or some good vector diagrams, or seeing an example.
> With the diagonal wire you're changing the current/magnetic sum vectors in
> direction and magnitude. The question is coming up with a current that
> reliably performs the cancellation function on the selected core of a
> bit-array while reliably *not* selecting another core, while accounting for
> all the variation tolerances in the array.
> >
> > While there's probably some value by which it would work in theory, I
> wonder whether the diagonal wire would narrow the operating margins. From
> some stuff I've seen, the hysteresis curves for cores weren't spectacularly
> square. With the usual 3D-3wire scheme of a close parallel inhibit wire you
> have 'cancellation by simplicity', you maximise the difference
> (cancellation) influence on one wire while minimising it's sum influence on
> the other.
> >
> > A related issue is the normal diagonal sense stringing (which this looks
> to have) has the wire entering the cores from both directions relative to
> the address wires, which is why sense amplifiers respond to pulses of both
> polarity. If this diagonal wire is put to use as an inhibit wire, some
> logic is needed to decide the direction of the inhibit current from the
> address, though that may not be very difficult.
> >
> > Some history of the 3-wire development might tell, whether inhibit was
> first applied to a diagonal sense stringing or whether sense was first
> applied to an adapted parallel-inhibit stringing. The real benefit of the
> 3-wire development was getting rid of the diagonal stringing for
> manufacturing ease.
> >
> >
> >>> There are a couple of Soviet core-rope memories up right now:
> >>>    https://www.ebay.com/itm/294558261336
> >>>    https://www.ebay.com/itm/294851032351
> >>
> >> Neat looking stuff.  It doesn't look like core rope memory in the sense
> of the AGC ROM, nor in the sense of the Electrologica X1.  It looks more
> like the transformer memory used in Wang calculators that you documented in
> your core ROM paper.
> >
> > Yes, (I was, perhaps lazily, slipping into the habit of referring to
> both forms (of woven-wire ROM) as rope).
>