Documentation for F11 Chipset?

[Rob Jarratt]

> -----Original Message-----
> From: cctalk <cctalk-bounces at classiccmp.org> On Behalf Of Bjoren Davis via
> cctalk
> Sent: 03 May 2021 20:45
> To: cctalk at classiccmp.org
> Subject: Re: Documentation for F11 Chipset?
> 
> Hello Paul and Rob,
> 
> The next thing I did was to hook up a logic analyzer to the address lines on
> the ROM.  This told me how far I got with the boot sequence before it
> restarted.
> 
> I disassembled the ROM and have some portions of it semi-decoded so that
> may be helpful.  If you like I can send you the text file I have.
> 
> Another helpful thing for me was to take the Xhomer emulator
> https://xhomer.isani.org/xhomer/ and instrument it to give me a "good"
> ROM boot sequence (correlated nicely with device accesses) and compare
> that with what I saw with my logic analyzer.
> 
> That's how I figured out my ROM was failing to see an interrupt from the EPCI
> (I think the ROM was running the EPCI in loopback mode) and so it was
> resetting.
> 
> I have to say: the POST on the PC3XX is impressively thorough, but the
> mechanism for reporting failures is absolutely atrocious (4 LEDs and, if you're
> lucky, a cryptic octal error code on the screen).
> 

In my case all the LEDs come on and stay on, so it isn't executing any instructions at all. I will look at the ROM next.

> I do have a functional 350 that I can instrument, so let me know if I can help.

If you get the opportunity I would be interested to know how the following signals look:

E22 pin 3
CT1 PT 4 (E22 pin 1)
CT1 PHASE L (E46 pin 8)

You can see how it looks for me here: https://rjarratt.files.wordpress.com/2021/05/bus-timeout-trace.png
Yellow: E22 pin 3
Cyan: CT1 PT 4 (E22 pin 1)
Pink: CT1 PHASE L (E46 pin 8)
Not shown is trigger off E70 pin 15.

> 
> --Bjoren
> 
> On 5/3/2021 2:29 PM, Paul Koning via cctalk wrote:
> >
> >> On May 3, 2021, at 2:23 PM, Rob Jarratt via cctalk <cctalk at classiccmp.org>
> wrote:
> >>
> >> Sadly my machine is not at the point where I can attach a console of any
> kind. The CPU is being reset every 13us by a bus error. I am having trouble
> working out why though. I have got as far as working out that is the CT2 TIME
> OUT signal, but just why that is active isn't entirely clear to me. It would help
> to have a working machine to compare it to!
> >>
> >> Regards
> >>
> >> Rob
> > That sounds like it's trying to access the boot ROM and not getting an
> answer.
> >
> > 	paul
> >
> >