PDP-11/70 debugging advice

[Josh Dersch]

On Sun, Jan 31, 2021 at 5:05 PM Fritz Mueller via cctalk <
cctalk at classiccmp.org> wrote:

> Hi Josh,
>
> ZAP is effectively reset for the micro-architecture, forcing the ucode
> address to known/initial value.  It has multiple sources throughout the
> processor, including tendrils into some of trap handling hardware. (Caveat:
> my experience is based off extensive work with the '11/45, but the
> micro-architecture as I understand it for the '11/70 is quite similar.)
>

Yeah, ZAP seems to be the entry point at power-up as well as for trap
handling.


> For the '45, there was a very handy "KB11-A,D Maintenance Manual", which
> explained the logic of such internal signals and the board by board
> internal operation of the CPU to a very useful level of detail; I'm sure
> similar is available for the KB11-B,C?  It's worth a read through if you
> haven't already, though its quite a bit to take in.
>

Yes, there's a similar doc.  The engineering drawings include the flow
diagrams for the microcode, and the Processor Manual (
http://bitsavers.org/pdf/dec/pdp11/1170/EK-KB11C-TM-001_1170procMan.pdf)
goes into details on the rest.  I started digesting all of this last night,
it's going to take awhile :).


>
> I would imagine the next step would be to throw the RAC board out on
> extenders, verify that ZAP is asserted, and if so pursue the driving source.
>

Yeah.  I want to get the fans installed and then go triple-check all the
power signals and get the voltages dialed in nicely.  But then things come
out on extenders :).


>
> Do you know if you have a KB11-B or C?
>

It's a KB11-C.


> Happy hunting!
>

Thanks, it'll be interesting for sure.
- Josh


>    --FritzM.
>
>
>